From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
To: Brian Cain <brian.cain@oss.qualcomm.com>, qemu-devel@nongnu.org
Subject: Re: [PATCH v3 5/5] tests/tcg/hexagon: check the two HVX predicate build paths agree
Date: Thu, 3 Sep 2026 22:51:03 -0700 [thread overview]
Message-ID: <e644d92e-8488-4e0d-b180-ccc35a448cef@oss.qualcomm.com> (raw)
In-Reply-To: <20260904012233.3607547-6-brian.cain@oss.qualcomm.com>
On 9/3/26 6:22 PM, Brian Cain wrote:
> A Q reg can be built by a vector compare or by vand(Vu, Rt), and
> those reach the predicate register through independent code paths. Check
> that both select the same byte lanes, so a byte-order mistake in either
> one is caught.
>
> The input alternates every eight lanes: a flatter pattern
> stays unchanged when predicate bytes are permuted and hides the bug.
>
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
> tests/tcg/hexagon/hvx_misc.c | 45 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
prev parent reply other threads:[~2026-09-04 5:51 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 1:22 [PATCH v3 0/5] hexagon: fix HVX scatter gather, BE host Brian Cain
2026-09-04 1:22 ` [PATCH v3 1/5] target/hexagon: fix HVX big-endian byte access Brian Cain
2026-09-04 1:22 ` [PATCH v3 2/5] target/hexagon: fix HVX scatter/gather region-length check Brian Cain
2026-09-04 10:33 ` Philippe Mathieu-Daudé
2026-09-04 22:22 ` Brian Cain
2026-09-04 1:22 ` [PATCH v3 3/5] tests/tcg/hexagon: add vgather/vscatter region-length tests Brian Cain
2026-09-04 5:50 ` Pierrick Bouvier
2026-09-04 1:22 ` [PATCH v3 4/5] target/hexagon: fix HVX predicate save size for histogram ops Brian Cain
2026-09-04 1:22 ` [PATCH v3 5/5] tests/tcg/hexagon: check the two HVX predicate build paths agree Brian Cain
2026-09-04 5:51 ` Pierrick Bouvier [this message]
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