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envelope-from=C.Koehne@beckhoff.com; helo=mx07-0090a401.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --=-+hOKFDcU7wpxfJSG9XA2 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Hi Peter, sry, for the late response. I've checked the manual [1]. 0xb70 is the right offset for R_DDRIOB_DCI_CTRL. Additionally, the correct reset value is 0x20= not 0x21. The commit also requires 0x20 as reset value because it tries to dete= ct a toggle of the reset bit (bit 0). Do you fix the commit or should we do it? Thanks for catching! [1] https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Register-slcr-DDRIOB_D= CI_CTRL --=20 Best regards, Corvin On Tue, 2026-07-07 at 11:58 +0100, Peter Maydell wrote: > Ping -- Corvin, Yannick, please could you suggest the right resolution > for this bug? >=20 > thanks > -- PMM >=20 >=20 > On Mon, 22 Jun 2026 at 15:49, Peter Maydell wr= ote: > >=20 > > On Fri, 29 May 2026 at 12:47, Peter Maydell > > wrote: > > >=20 > > > From: YannickV > > >=20 > > > The registers for the digitally controlled impedance (DCI) clock are > > > part of the system level control registers (SLCR). The DONE bit in > > > the status register indicates a successfull DCI calibration. An > > > description of the calibration process can be found here: > > > https://urldefense.com/v3/__https://docs.amd.com/r/en-US/ug585-zynq-7= 000-SoC-TRM/DDR-IOB-Impedance-Calibration__;!!PlYMe_wG1g!lthDLWtCQd7a8JMN8G= 4iIPO8hmKqHg5ON9qsiI2YQGx5fTuThS3u5WwV6IeiZCeJf2gNSKMWSZ2wKu91Kb6gVFdpPQ$ > > >=20 > > > The DCI control register and status register have been added. As soon > > > as the ENABLE and RESET bit are set, the RESET bit has also been togg= led > > > to 0 before and the UPDATE_CONTROL is not set, the DONE bit in the st= atus > > > register is set. If these bits change the DONE bit is reset. Note tha= t the > > > option bits are not taken into consideration. > >=20 > > Hi; we've just had a Coverity Scan run that went over this code, > > and it points out an issue: > >=20 > > > =C2=A0REG32(DDRIOB, 0xb40) > > > +REG32(DDRIOB_DCI_CTRL, 0xb70) > >=20 > > These REG32() macros define R_DDRIOB as 0xb40 / 4 =3D=3D 0x2d0, > > and R_DDRIOB_DCI_CTRL as 0xb70 / 4 =3D=3D 0x2dc... > >=20 > > > @@ -418,6 +428,8 @@ static void zynq_slcr_reset_init(Object *obj, > > > ResetType type) > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0s->regs[R_DDRIOB + 4] =3D s->regs[R_DDR= IOB + 5] =3D s->regs[R_DDRIOB + 6] > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=3D 0x00000e00; > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0s->regs[R_DDRIOB + 12] =3D 0x00000021; > > > + > > > + s->regs[R_DDRIOB_DCI_CTRL] =3D 0x00000020; > >=20 > > ...and here in the reset function we are now initializing > > both s->regs[R_DDRIOB + 12] and s->regs[R_DDRIOB_DCI_CTRL], but > > those are the same array element (since 0x2d0 + 12 =3D=3D 0x2dc). > >=20 > > What was the intention here? Which reset value is correct? > > Should we be resetting some other register where we currently > > are resetting s->regs[R_DDRIOB + 12] ? > >=20 > > thanks > > -- PMM This email contains confidential information. If you have received it in er= ror, you must not read, use, copy or pass on this e-mail or its attachments. If you have received the e-mail in error, please inform me immediately by r= eply e-mail and then delete this e-mail from your system. Thank you Diese E-Mail enth=C3=A4lt vertrauliche Informationen. Sollten Sie sie irrt= =C3=BCmlich erhalten haben, d=C3=BCrfen Sie diese E-Mail oder ihre Anh=C3= =A4nge nicht lesen, verwenden, kopieren oder weitergeben. Sollten Sie die Mail versehentlich erhalten haben, teilen Sie mir dies bitt= e umgehend per Antwort-E-Mail mit und l=C3=B6schen Sie diese E-Mail dann au= s Ihrem System. Vielen Dank Beckhoff Automation GmbH & Co. KG=20 Managing Director: Dipl. Phys. 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