From: Oleksii Kurochko <oleksii.kurochko@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "Romain Caritey" <Romain.Caritey@microchip.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Connor Davis" <connojdavis@gmail.com>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Anthony PERARD" <anthony.perard@vates.tech>,
"Michal Orzel" <michal.orzel@amd.com>,
"Julien Grall" <julien@xen.org>,
"Roger Pau Monné" <roger.pau@citrix.com>,
"Stefano Stabellini" <sstabellini@kernel.org>,
xen-devel@lists.xenproject.org
Subject: Re: [PATCH v3 04/16] xen/riscv: implement vcpu_csr_init()
Date: Wed, 11 Feb 2026 10:53:01 +0100 [thread overview]
Message-ID: <e7475d33-a7ca-4095-9483-e23a8587850f@gmail.com> (raw)
In-Reply-To: <fa58fd77-b513-4704-8598-1209b55226a3@suse.com>
On 2/11/26 10:44 AM, Jan Beulich wrote:
> On 09.02.2026 17:52, Oleksii Kurochko wrote:
>> --- a/xen/arch/riscv/domain.c
>> +++ b/xen/arch/riscv/domain.c
>> @@ -5,6 +5,72 @@
>> #include <xen/sched.h>
>> #include <xen/vmap.h>
>>
>> +#include <asm/cpufeature.h>
>> +#include <asm/csr.h>
>> +#include <asm/riscv_encoding.h>
>> +#include <asm/setup.h>
>> +
>> +#define HEDELEG_DEFAULT (BIT(CAUSE_MISALIGNED_FETCH, U) | \
>> + BIT(CAUSE_FETCH_ACCESS, U) | \
>> + BIT(CAUSE_ILLEGAL_INSTRUCTION, U) | \
>> + BIT(CAUSE_BREAKPOINT, U) | \
>> + BIT(CAUSE_MISALIGNED_LOAD, U) | \
>> + BIT(CAUSE_LOAD_ACCESS, U) | \
>> + BIT(CAUSE_MISALIGNED_STORE, U) | \
>> + BIT(CAUSE_STORE_ACCESS, U) | \
>> + BIT(CAUSE_USER_ECALL, U) | \
>> + BIT(CAUSE_FETCH_PAGE_FAULT, U) | \
>> + BIT(CAUSE_LOAD_PAGE_FAULT, U) | \
>> + BIT(CAUSE_STORE_PAGE_FAULT, U))
>> +
>> +#define HIDELEG_DEFAULT (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
>> +
>> +static void vcpu_csr_init(struct vcpu *v)
>> +{
>> + register_t hstateen0;
> There not being an initializer here, ...
>
>> + v->arch.hedeleg = HEDELEG_DEFAULT & csr_masks.hedeleg;
>> +
>> + vcpu_guest_cpu_user_regs(v)->hstatus = HSTATUS_SPV | HSTATUS_SPVP;
>> +
>> + v->arch.hideleg = HIDELEG_DEFAULT & csr_masks.hideleg;
>> +
>> + /*
>> + * VS should access only the time counter directly.
>> + * Everything else should trap.
>> + */
>> + v->arch.hcounteren = HCOUNTEREN_TM;
>> +
>> + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svpbmt) )
>> + v->arch.henvcfg = ENVCFG_PBMTE & csr_masks.henvcfg;
>> +
>> + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) )
>> + {
>> + if (riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ssaia))
> (Nit: Style.)
>
>> + /*
>> + * If the hypervisor extension is implemented, the same three
>> + * bitsare defined also in hypervisor CSR hstateen0 but concern
> (Nit: "bits are")
>
>> + * only the state potentially accessible to a virtual machine
>> + * executing in privilege modes VS and VU:
>> + * bit 60 CSRs siselect and sireg (really vsiselect and
>> + * vsireg)
>> + * bit 59 CSRs siph and sieh (RV32 only) and stopi (really
>> + * vsiph, vsieh, and vstopi)
>> + * bit 58 all state of IMSIC guest interrupt files, including
>> + * CSR stopei (really vstopei)
>> + * If one of these bits is zero in hstateen0, and the same bit is
>> + * one in mstateen0, then an attempt to access the corresponding
>> + * state from VS or VU-mode raises a virtual instruction exception.
>> + */
>> + hstateen0 = SMSTATEEN0_AIA | SMSTATEEN0_IMSIC | SMSTATEEN0_SVSLCT;
>> +
>> + /* Allow guest to access CSR_ENVCFG */
>> + hstateen0 |= SMSTATEEN0_HSENVCFG;
> ... doesn't the compiler complain about the use of a possibly uninitialized
> variable? The variable also wants to move to the more narrow scope.
Hmm, for some reason it doesn't. Anyway, I agree that it would be better to move
it to a narrower scope, since `hstateen0` exists only when RISCV_ISA_EXT_smstateen
is supported.
>
>> @@ -32,6 +98,8 @@ int arch_vcpu_create(struct vcpu *v)
>> v->arch.xen_saved_context.sp = (register_t)v->arch.cpu_info;
>> v->arch.xen_saved_context.ra = (register_t)continue_new_vcpu;
>>
>> + vcpu_csr_init(v);
>> +
>> /* Idle VCPUs don't need the rest of this setup */
>> if ( is_idle_vcpu(v) )
>> return rc;
> Do idle vCPU-s really need to have vcpu_csr_init() called for them?
Agree, there is no any sense. I will move the call of vcpu_csr_init() after
is_idle_vcpu() check.
Thanks.
~ Oleksii
next prev parent reply other threads:[~2026-02-11 9:53 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-09 16:52 [PATCH v3 00/16] xen/riscv: introduce vtimer related things Oleksii Kurochko
2026-02-09 16:52 ` [PATCH v3 01/16] xen/riscv: implement arch_vcpu_{create,destroy}() Oleksii Kurochko
2026-02-10 16:24 ` Jan Beulich
2026-02-09 16:52 ` [PATCH v3 02/16] xen/riscv: avoid reading hstateen0 when Smstateen is not implemented Oleksii Kurochko
2026-02-11 7:22 ` Jan Beulich
2026-02-11 8:45 ` Oleksii Kurochko
2026-02-09 16:52 ` [PATCH v3 03/16] xen/riscv: detect and store supported hypervisor CSR bits at boot Oleksii Kurochko
2026-02-11 7:49 ` Jan Beulich
2026-02-11 9:47 ` Oleksii Kurochko
2026-02-11 9:50 ` Jan Beulich
2026-02-09 16:52 ` [PATCH v3 04/16] xen/riscv: implement vcpu_csr_init() Oleksii Kurochko
2026-02-11 9:44 ` Jan Beulich
2026-02-11 9:53 ` Oleksii Kurochko [this message]
2026-02-09 16:52 ` [PATCH v3 05/16] xen/riscv: introduce tracking of pending vCPU interrupts, part 1 Oleksii Kurochko
2026-02-11 14:16 ` Jan Beulich
2026-02-11 14:53 ` Jan Beulich
2026-02-12 9:37 ` Oleksii Kurochko
2026-02-12 10:24 ` Jan Beulich
2026-02-12 11:23 ` Oleksii Kurochko
2026-02-09 16:52 ` [PATCH v3 06/16] xen/riscv: introduce tracking of pending vCPU interrupts, part 2 Oleksii Kurochko
2026-02-11 14:26 ` Jan Beulich
2026-02-11 15:59 ` Oleksii Kurochko
2026-02-09 16:52 ` [PATCH v3 07/16] xen/time: move ticks<->ns helpers to common code Oleksii Kurochko
2026-02-09 16:52 ` [PATCH v3 08/16] xen/riscv: introduce basic vtimer infrastructure for guests Oleksii Kurochko
2026-02-11 14:51 ` Jan Beulich
2026-02-11 15:31 ` Oleksii Kurochko
2026-02-09 16:52 ` [PATCH v3 09/16] xen/riscv: introduce vcpu_kick() implementation Oleksii Kurochko
2026-02-09 16:52 ` [PATCH v3 10/16] xen/riscv: add vtimer context switch helpers Oleksii Kurochko
2026-02-09 16:52 ` [PATCH v3 11/16] xen/riscv: implement SBI legacy SET_TIMER support for guests Oleksii Kurochko
2026-02-09 16:52 ` [PATCH v3 12/16] xen/riscv: introduce sbi_set_timer() Oleksii Kurochko
2026-02-11 15:03 ` Jan Beulich
2026-02-11 15:37 ` Oleksii Kurochko
2026-02-09 16:52 ` [PATCH v3 13/16] xen/riscv: implement reprogram_timer() via SBI Oleksii Kurochko
2026-02-11 15:12 ` Jan Beulich
2026-02-11 15:14 ` Jan Beulich
2026-02-09 16:52 ` [PATCH v3 14/16] xen/riscv: handle hypervisor timer interrupts Oleksii Kurochko
2026-02-09 16:52 ` [PATCH v3 15/16] xen/riscv: init tasklet subsystem Oleksii Kurochko
2026-02-09 16:52 ` [PATCH v3 16/16] xen/riscv: implement sync_vcpu_execstate() Oleksii Kurochko
2026-02-11 15:16 ` Jan Beulich
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