From: Simon Marchi <simon.marchi@polymtl.ca>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])
Date: Sun, 08 Oct 2017 10:06:20 -0400 [thread overview]
Message-ID: <e757489a1343720d22d2ec33518fac4c@polymtl.ca> (raw)
In-Reply-To: <20171008122357.GA2958@lianli.shorne-pla.net>
On 2017-10-08 08:23, Stafford Horne wrote:
>> > + if (n.normal_exp < -1) /* If n looks like zero just return l. */
>> > + {
>> > + *f = *l;
>> > + return 0;
>> > + }
>> > + else if (n.class == sim_fpu_class_number
>> > + && n.normal_exp <= (NR_FRAC_GUARD)) /* If not too large round. */
>>
>> This line should be aligned with the opening parenthesis (well, one
>> char to the right).
>
> Right, that does move the comment out of the 80 char range, but just
> the
> ending '*/'. I hope thats ok.
Hmm, when I try it the trailing */ arrives right before the 80th column.
Simon
next prev parent reply other threads:[~2017-10-08 14:06 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-05 13:49 [OpenRISC] [PATCH v5 0/6] sim port for OpenRISC Stafford Horne
2017-10-05 13:49 ` [OpenRISC] [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd]) Stafford Horne
2017-10-07 15:52 ` Simon Marchi
2017-10-08 12:23 ` Stafford Horne
2017-10-08 14:06 ` Simon Marchi [this message]
2017-10-05 13:49 ` [OpenRISC] [PATCH v5 2/6] sim: cgen: add MUL2OFSI and MUL1OFSI macros (needed for OR1K l.mul[u]) Stafford Horne
2017-10-07 16:00 ` Simon Marchi
2017-10-08 12:27 ` Stafford Horne
2017-10-05 13:49 ` [OpenRISC] [PATCH v5 3/6] sim: or1k: add or1k target to sim Stafford Horne
2017-10-07 21:14 ` Simon Marchi
2017-10-09 13:03 ` Stafford Horne
2017-10-09 13:33 ` Simon Marchi
2017-10-05 13:49 ` [OpenRISC] [PATCH v5 4/6] sim: or1k: add cgen generated files Stafford Horne
2017-10-05 13:49 ` [OpenRISC] [PATCH v5 5/6] sim: or1k: add autoconf " Stafford Horne
2017-10-05 13:49 ` [OpenRISC] [PATCH v5 6/6] sim: testsuite: add testsuite for or1k sim Stafford Horne
2017-10-05 13:57 ` [OpenRISC] [PATCH v5 0/6] sim port for OpenRISC Stafford Horne
2017-10-05 14:23 ` Stafford Horne
-- strict thread matches above, loose matches on Subject: below --
2017-10-09 17:00 [OpenRISC] [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd]) Doug Evans
2017-10-09 17:01 Doug Evans
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