Re: [PATCH] Change timer interrupt to edge sensitive

[Dinh Nguyen <dinguyen@kernel.org>]

On 08/07/2018 05:03 PM, Thor Thayer wrote:
> Hi Silvan,
> 
> On 08/07/2018 02:23 PM, Silvan Murer wrote:
>> Hi Thor,
>>
>> Did you saw my patch? I think the default configuration for the timer
>> interrupt should be <1 13 0xf01>
>>
>> Otherwise, the driver get the error "GIC: PPI13 is secure or
>> misconfigured"
>>
>> Base on the ARM documentation it is a edge sensitive trigger:
>> http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407f/CCHEIGIC.html
>>
>> Or do I understand something wrong?
>>
> This looks correct. In fact, our socfpga.dtsi base file uses the rising
> edge.
> 
>> Best regards,
>> Silvan
>>
>>
>> On 02.08.2018 13:41, Silvan Murer wrote:
>>> Signed-off-by: Silvan Murer <silvan.murer@gmail.com>
>>> ---
>>>   arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi
>>> b/arch/arm/boot/dts/socfpga_arria10.dtsi
>>> index 791ca15..52a7025 100644
>>> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
>>> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
>>> @@ -748,7 +748,7 @@
>>>           timer@ffffc600 {
>>>               compatible = "arm,cortex-a9-twd-timer";
>>>               reg = <0xffffc600 0x100>;
>>> -            interrupts = <1 13 0xf04>;
>>> +            interrupts = <1 13 0xf01>;
>>>               clocks = <&mpu_periph_clk>;
>>>           };
>>>   
>>
> Reviewed-by: Thor Thayer <thor.thayer@linux.intel.com>
> 

Applied!

Thanks,
Dinh