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envelope-from=asahu1x@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 27/08/26 6:59 PM, Chinmay Rath wrote: > This series primarily contains 3 changes : > > 1. PPC instructions movement to decodetree specification > Changes from v2 : > - Addressed review comments from Amit, as discussed in the v2 series. > - Retained Rbs received. > > 2. PPC ISA 2.07 flag cleanup and updates > This series is based on top the above decodetree series. > - No changes. Only Rbs added. > > 3. Stepping up as an active maintainer for PowerPC TCG CPUs module. > > Link to v2: https://lore.kernel.org/qemu-devel/20260826050923.74756-1-rathc@linux.ibm.com/ > > Aboorva Devarajan (3): > target/ppc: Move vector merge instructions to decodetree > target/ppc: Move vector pack instructions to decodetree > target/ppc: Move GPR atomic load/store instructions to decodetree > > Amit Machhiwal (2): > target/ppc: Move fixed-point Shift insns to decodetree > target/ppc: Move fixed-point byte-reversal store insns to decodetree > > Chinmay Rath (9): > target/ppc: make do_ea_calc_ra available for 32 bit builds > target/ppc: Replace PPC2_VSX207 flag with PPC2_ISA207 > target/ppc: Use PPC2_ISA207 instead of PPC2_BCTAR_ISA207 > target/ppc: Use PPC2_ISA207 instead of PPC2_LSQ_ISA207 > target/ppc: Use PPC2_ISA207 instead of PPC2_ALTIVEC_207 > target/ppc: Use PPC2_ISA207 instead of PPC2_ISA207S > target/ppc: Reorder PPC2 flags > target/ppc: Add ICBT support for ISA version 2.07 > target/ppc: Add self as maintainer for PowerPC TCG CPUs > > Mukesh Kumar Chaurasiya (IBM) (2): > target/ppc: convert slw, srw instruction via decode spec > target/ppc: convert sraw[i] instruction via decode spec > > Nikhil Kumar Singh (3): > target/ppc: Migrate extswsli to decodetree > target/ppc: Migrate atomic loads to decodetree > target/ppc: Convert cache instructions to decodetree > > Ojaswin Mujoo (7): > target/ppc: Move isync instruction to decodetree > target/ppc: Convert b{a, l, la} to decode tree > target/ppc: move various conditional branch insns to decodetree > target/ppc: Fix TRANS* macro variadic arguments handling > target/ppc: Move wait instruction to decodetree > target/ppc: Move sleep & friends to decodetree > target/ppc: Refactor sleep and its variants to use a common helper > > Shivang Upadhyay (4): > target/ppc: Move Condition Register access instructions to decodetree. > target/ppc: Move Condition Register logical instructions to > decodetree. > target/ppc: Move Fixed-Point Load/Store String instructions to > decodetree. > target/ppc: Move VMX integer arithmetic and BCD instructions to > decodetree. > > Shivani Nittor (1): > target/ppc: Convert mcrf to decode tree > > Tanushree Shah (2): > target/ppc: Move rlwimi, rlwinm instructions to decodetree > target/ppc: Move lmw, stmw instructions to decodetree > > Utkarsh Verma (1): > target/ppc: Move st{b, h, w, d, q}cx instructions to decodetree > > Vishal Chourasia (3): > target/ppc: Move mfmsr, mtmsr[d] instructions to decodetree > target/ppc: Move byte-reverse instructions to decodetree > target/ppc: Move system call and rfi instructions to decodetree Ran my tests on the v3 patch, here are the findings: - Built qemu with all 37 patches applied with no issues - All relevant selftests are passing without errors - Guest boots and runs in TCG mode, checked with SLES16.1 RC2 guest on an Ubuntu 26.10 host - Basic functionality checks done for guest, no issues found Tested-by: Aniket Sahu > > MAINTAINERS | 2 +- > hw/ppc/spapr_caps.c | 2 +- > linux-user/ppc/elfload.c | 6 +- > target/ppc/cpu.h | 38 +- > target/ppc/cpu_init.c | 6 +- > target/ppc/cpu_init.h | 7 +- > target/ppc/helper.h | 96 +- > target/ppc/insn32.decode | 252 ++ > target/ppc/int_helper.c | 76 +- > target/ppc/internal.h | 7 - > target/ppc/mem_helper.c | 14 +- > target/ppc/tcg-excp_helper.c | 18 +- > target/ppc/translate.c | 2258 +++-------------- > target/ppc/translate/bhrb-impl.c.inc | 4 +- > target/ppc/translate/branch-impl.c.inc | 182 +- > target/ppc/translate/fixedpoint-impl.c.inc | 947 ++++++- > target/ppc/translate/fp-impl.c.inc | 4 +- > target/ppc/translate/misc-impl.c.inc | 172 ++ > .../ppc/translate/processor-ctrl-impl.c.inc | 39 +- > target/ppc/translate/storage-ctrl-impl.c.inc | 116 + > target/ppc/translate/vmx-impl.c.inc | 457 ++-- > target/ppc/translate/vmx-ops.c.inc | 59 +- > target/ppc/translate/vsx-impl.c.inc | 56 +- > target/ppc/translate/vsx-ops.c.inc | 24 +- > 24 files changed, 2473 insertions(+), 2369 deletions(-) >