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From: Christian Bruel <christian.bruel@foss.st.com>
To: Bjorn Helgaas <helgaas@kernel.org>,
	Linus Walleij <linus.walleij@linaro.org>
Cc: <lpieralisi@kernel.org>, <kwilczynski@kernel.org>,
	<mani@kernel.org>, <robh@kernel.org>, <bhelgaas@google.com>,
	<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
	<mcoquelin.stm32@gmail.com>, <alexandre.torgue@foss.st.com>,
	<p.zabel@pengutronix.de>, <johan+linaro@kernel.org>,
	<cassel@kernel.org>, <shradha.t@samsung.com>,
	<thippeswamy.havalige@amd.com>, <quic_schintav@quicinc.com>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-stm32@st-md-mailman.stormreply.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v12 2/9] PCI: stm32: Add PCIe host support for STM32MP25
Date: Fri, 8 Aug 2025 16:55:52 +0200	[thread overview]
Message-ID: <e7cd764d-bc6d-4e39-aa03-0eee8e30d3e5@foss.st.com> (raw)
In-Reply-To: <20250807180951.GA56737@bhelgaas>



On 8/7/25 20:09, Bjorn Helgaas wrote:
> [+to Linus for pinctrl usage question below]
> 
> On Tue, Jun 10, 2025 at 11:07:07AM +0200, Christian Bruel wrote:
>> Add driver for the STM32MP25 SoC PCIe Gen1 2.5 GT/s and Gen2 5GT/s
>> controller based on the DesignWare PCIe core.
>>

>> +
>> +	return pinctrl_pm_select_sleep_state(dev);
> 
> Isn't there some setup required before we can use
> pinctrl_select_state(), pinctrl_pm_select_sleep_state(),
> pinctrl_pm_select_default_state(), etc?
> 
> I expected something like devm_pinctrl_get() in the .probe() path, but
> I don't see anything.  I don't know how pinctrl works, but I don't see
> how dev->pins gets set up.

Linus knows better, but the dev->pins states are attached to the dev 
struct before probe by the pinctrl driver

/**
  * pinctrl_bind_pins() - called by the device core before probe
  * @dev: the device that is just about to probe
  */
int pinctrl_bind_pins(struct device *dev)

Christian


  reply	other threads:[~2025-08-08 15:05 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-10  9:07 [PATCH v12 0/9] Add STM32MP25 PCIe drivers Christian Bruel
2025-06-10  9:07 ` [PATCH v12 1/9] dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings Christian Bruel
2025-06-10  9:07 ` [PATCH v12 2/9] PCI: stm32: Add PCIe host support for STM32MP25 Christian Bruel
2025-08-07 18:09   ` Bjorn Helgaas
2025-08-08 14:55     ` Christian Bruel [this message]
2025-08-08 16:45       ` Bjorn Helgaas
2025-08-11 13:30         ` Christian Bruel
2025-08-13 19:29   ` Bjorn Helgaas
2025-08-18 10:50     ` Christian Bruel
2025-08-18 23:06       ` Bjorn Helgaas
2025-08-19 13:01         ` Christian Bruel
2025-06-10  9:07 ` [PATCH v12 3/9] dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings Christian Bruel
2025-06-10  9:07 ` [PATCH v12 4/9] PCI: stm32: Add PCIe Endpoint support for STM32MP25 Christian Bruel
2025-06-10  9:07 ` [PATCH v12 5/9] MAINTAINERS: add entry for ST STM32MP25 PCIe drivers Christian Bruel
2025-06-10  9:07 ` [PATCH v12 6/9] arm64: dts: st: add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi Christian Bruel
2025-06-10  9:07 ` [PATCH v12 7/9] arm64: dts: st: Add PCIe Root Complex mode on stm32mp251 Christian Bruel
2025-06-23 12:15   ` Manivannan Sadhasivam
2025-06-10  9:07 ` [PATCH v12 8/9] arm64: dts: st: Add PCIe Endpoint " Christian Bruel
2025-06-23 12:15   ` Manivannan Sadhasivam
2025-06-10  9:07 ` [PATCH v12 9/9] arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board Christian Bruel
2025-06-23 12:13 ` (subset) [PATCH v12 0/9] Add STM32MP25 PCIe drivers Manivannan Sadhasivam
2025-06-24 22:22   ` Bjorn Helgaas
2025-06-25  4:00     ` Manivannan Sadhasivam
2025-06-25 10:18       ` Christian Bruel
2025-06-25 13:09         ` Manivannan Sadhasivam

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