From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-182.mta0.migadu.com (out-182.mta0.migadu.com [91.218.175.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A1F027935A for ; Tue, 1 Jul 2025 16:20:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.182 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751386860; cv=none; b=czJKvEJ8O4Z+HGi9cMCxQRWh+tfRN/bz//hW135phjhg+y26wRkkKHUDUIre/1XXjFIPr/2TNSOs7m0Psrdaex68xmvhnfjeAfFGyZIMldfCwsmC3579jFZt8d7XQ+F+5YEc9jjLjCmaadmMiuEN5YEgAHF2PVDH8fBLdhxGcoA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751386860; c=relaxed/simple; bh=HQktoeVlNcl4UkDcYQChN8gXI5vAV3mCyQeSK5m9Tfk=; h=Message-ID:Date:MIME-Version:Subject:From:To:Cc:References: In-Reply-To:Content-Type; b=IgKl428fhzwXeF1J0FXtfu5/C4Iap8mPpIMVERaDmqud1GQXXbdxGk/kM7d8mVWp0tKsafJ98y4bOUiy7lXnQoLghsIm7olMx4FnDiGIUK7DETkjrH2m9RVkbbFrBkq/nDjleoKvR3HgF8oIKQEcvpBBd4ceipIkFeEw24xnvO4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=JIZv0vZl; arc=none smtp.client-ip=91.218.175.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="JIZv0vZl" Message-ID: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1751386846; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=e1/e3eap9f2tDNMMl9IjOF9XHUaDUuipryrarrhqc5k=; b=JIZv0vZlClHXgj7127g8+kz2SRAr0Px3UoYls6ptGkhWdbdq2YobumRaWhdMF90BjQSxlp eXwOfHeMmjmbjKXoX7xNNU7RaeiDHkSB6FrpfzvEPDyPkkC38h9m2xx7Bg2U7vQvBCj3tq bWXWe1kLdjto2uFwDP38VDeu9Vk92Qc= Date: Tue, 1 Jul 2025 12:20:37 -0400 Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH net-next v2 10/18] net: macb: remove illusion about TBQPH/RBQPH being per-queue X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Sean Anderson To: =?UTF-8?Q?Th=C3=A9o_Lebrun?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Samuel Holland , Richard Cochran , Russell King , Thomas Bogendoerfer , Vladimir Kondratiev , Gregory CLEMENT , Cyrille Pitchen , Harini Katakam , Rafal Ozieblo , Haavard Skinnemoen , Jeff Garzik Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-mips@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk References: <20250627-macb-v2-0-ff8207d0bb77@bootlin.com> <20250627-macb-v2-10-ff8207d0bb77@bootlin.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT On 7/1/25 12:15, Sean Anderson wrote: > On 6/27/25 05:08, Théo Lebrun wrote: >> The MACB driver acts as if TBQPH/RBQPH are configurable on a per queue >> basis; this is a lie. A single register configures the upper 32 bits of >> each DMA descriptor buffers for all queues. >> >> Concrete actions: >> >> - Drop GEM_TBQPH/GEM_RBQPH macros which have a queue index argument. >> Only use MACB_TBQPH/MACB_RBQPH constants. >> >> - Drop struct macb_queue->TBQPH/RBQPH fields. >> >> - In macb_init_buffers(): do a single write to TBQPH and RBQPH for all >> queues instead of a write per queue. >> >> - In macb_tx_error_task(): drop the write to TBQPH. >> >> - In macb_alloc_consistent(): if allocations give different upper >> 32-bits, fail. Previously, it would have lead to silent memory >> corruption as queues would have used the upper 32 bits of the alloc >> from queue 0 and their own low 32 bits. > > While better than silent memory corruption, this is not a good solution > since bringing the netdev up will now randomly fail. Can we allocate the > rings in one contiguous chunk instead? Ah, looks like you do this in the next patch. In that case, (with the other comments addressed) Reviewed-by: Sean Anderson >> - In macb_suspend(): if we use the tie off descriptor for suspend, do >> the write once for all queues instead of once per queue. >> >> Fixes: fff8019a08b6 ("net: macb: Add 64 bit addressing support for GEM") >> Fixes: ae1f2a56d273 ("net: macb: Added support for many RX queues") >> Signed-off-by: Théo Lebrun > > As this is a bugfix, can you move it before your cleanup patches? This > will make it easier to backport to stable kernels. > >> --- >> drivers/net/ethernet/cadence/macb.h | 4 ---- >> drivers/net/ethernet/cadence/macb_main.c | 36 +++++++++++++------------------- >> 2 files changed, 14 insertions(+), 26 deletions(-) >> >> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h >> index 707b3286a6b8408a3bc4bbbcb1335ae8c3cd95ad..adc70b6efd52b0b11e436c2c95bb5108c40f3490 100644 >> --- a/drivers/net/ethernet/cadence/macb.h >> +++ b/drivers/net/ethernet/cadence/macb.h >> @@ -209,10 +209,8 @@ >> >> #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2)) >> #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2)) >> -#define GEM_TBQPH(hw_q) (0x04C8) >> #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2)) >> #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2)) >> -#define GEM_RBQPH(hw_q) (0x04D4) >> #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2)) >> #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2)) >> #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2)) >> @@ -1208,10 +1206,8 @@ struct macb_queue { >> unsigned int IDR; >> unsigned int IMR; >> unsigned int TBQP; >> - unsigned int TBQPH; >> unsigned int RBQS; >> unsigned int RBQP; >> - unsigned int RBQPH; >> >> /* Lock to protect tx_head and tx_tail */ >> spinlock_t tx_ptr_lock; >> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c >> index a6633e076644089c796453f856a766299bae2ec6..d3b3635998cad095246edf8a75faebbcf7115355 100644 >> --- a/drivers/net/ethernet/cadence/macb_main.c >> +++ b/drivers/net/ethernet/cadence/macb_main.c >> @@ -482,15 +482,15 @@ static void macb_init_buffers(struct macb *bp) >> struct macb_queue *queue; >> unsigned int q; >> >> + if (macb_dma_is_64b(bp)) { >> + /* Single register for all queues' high 32 bits. */ >> + macb_writel(bp, RBQPH, upper_32_bits(bp->queues->rx_ring_dma)); >> + macb_writel(bp, TBQPH, upper_32_bits(bp->queues->tx_ring_dma)); >> + } >> + >> for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { >> queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma)); >> - if (macb_dma_is_64b(bp)) >> - queue_writel(queue, RBQPH, >> - upper_32_bits(queue->rx_ring_dma)); >> queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); >> - if (macb_dma_is_64b(bp)) >> - queue_writel(queue, TBQPH, >> - upper_32_bits(queue->tx_ring_dma)); >> } >> } >> >> @@ -1145,8 +1145,6 @@ static void macb_tx_error_task(struct work_struct *work) >> >> /* Reinitialize the TX desc queue */ >> queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); >> - if (macb_dma_is_64b(bp)) >> - queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma)); >> /* Make TX ring reflect state of hardware */ >> queue->tx_head = 0; >> queue->tx_tail = 0; >> @@ -2524,7 +2522,8 @@ static int macb_alloc_consistent(struct macb *bp) >> queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, >> &queue->tx_ring_dma, >> GFP_KERNEL); >> - if (!queue->tx_ring) >> + if (!queue->tx_ring || >> + upper_32_bits(queue->tx_ring_dma) != upper_32_bits(bp->queues->tx_ring_dma)) >> goto out_err; >> netdev_dbg(bp->dev, >> "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n", >> @@ -2539,7 +2538,8 @@ static int macb_alloc_consistent(struct macb *bp) >> size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch; >> queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, >> &queue->rx_ring_dma, GFP_KERNEL); >> - if (!queue->rx_ring) >> + if (!queue->rx_ring || >> + upper_32_bits(queue->rx_ring_dma) != upper_32_bits(bp->queues->rx_ring_dma)) > > Can you write this as bp->queues[0].rx_ring_dma for clarity? > >> goto out_err; >> netdev_dbg(bp->dev, >> "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", >> @@ -4269,10 +4269,6 @@ static int macb_init(struct platform_device *pdev) >> queue->TBQP = GEM_TBQP(hw_q - 1); >> queue->RBQP = GEM_RBQP(hw_q - 1); >> queue->RBQS = GEM_RBQS(hw_q - 1); >> - if (macb_dma_is_64b(bp)) { >> - queue->TBQPH = GEM_TBQPH(hw_q - 1); >> - queue->RBQPH = GEM_RBQPH(hw_q - 1); >> - } >> } else { >> /* queue0 uses legacy registers */ >> queue->ISR = MACB_ISR; >> @@ -4281,10 +4277,6 @@ static int macb_init(struct platform_device *pdev) >> queue->IMR = MACB_IMR; >> queue->TBQP = MACB_TBQP; >> queue->RBQP = MACB_RBQP; >> - if (macb_dma_is_64b(bp)) { >> - queue->TBQPH = MACB_TBQPH; >> - queue->RBQPH = MACB_RBQPH; >> - } >> } >> >> /* get irq: here we use the linux queue index, not the hardware >> @@ -5401,6 +5393,10 @@ static int __maybe_unused macb_suspend(struct device *dev) >> */ >> tmp = macb_readl(bp, NCR); >> macb_writel(bp, NCR, tmp & ~(MACB_BIT(TE) | MACB_BIT(RE))); >> +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT >> + if (!(bp->caps & MACB_CAPS_QUEUE_DISABLE)) >> + macb_writel(bp, RBQPH, upper_32_bits(bp->rx_ring_tieoff_dma)); >> +#endif >> for (q = 0, queue = bp->queues; q < bp->num_queues; >> ++q, ++queue) { >> /* Disable RX queues */ >> @@ -5410,10 +5406,6 @@ static int __maybe_unused macb_suspend(struct device *dev) >> /* Tie off RX queues */ >> queue_writel(queue, RBQP, >> lower_32_bits(bp->rx_ring_tieoff_dma)); >> -#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT >> - queue_writel(queue, RBQPH, >> - upper_32_bits(bp->rx_ring_tieoff_dma)); >> -#endif >> } >> /* Disable all interrupts */ >> queue_writel(queue, IDR, -1); >> From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D163C7EE30 for ; Tue, 1 Jul 2025 19:00:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:References:Cc:To:From: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fdv9+pz6tKo52xScj2qNQBL/pSVH8BKwo20X5MXcRwA=; b=Zxri1WFCTRTXzv XKosrfBhW0GPGmKqyRQOKiJujcsz1nTAolSe3mM5fVerD+F2lBG5q4RtlqnrQ6BiMJGd8EfAEtzm+ y+nVz1HdRfw4+QIX5lJcLhZYhxNA8tWD7bHioxZ8oA7IwVne9/cjyGieQ4fqv5EImVbZF1rssrcNx vfj9jNyjvFhiHVtennb8/aEtRGfWj1d0ekAEKW00qORz6R8QV6rtQaOIZmTtsmVnOQNdi5KS61xLp Y0d68LQStN3EKH42Sz07zkrlcxIe4xNNdP7Z6c6F9eA0VEFDwAHeTRqaPRfY7EI+3g9fyCRSNy3M8 ImWYLQmS0mJqD0Prwguw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uWgDP-00000006PB4-0f85; Tue, 01 Jul 2025 19:00:23 +0000 Received: from out-180.mta0.migadu.com ([2001:41d0:1004:224b::b4]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uWdiz-0000000618e-13CC for linux-riscv@lists.infradead.org; Tue, 01 Jul 2025 16:20:50 +0000 Message-ID: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1751386846; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=e1/e3eap9f2tDNMMl9IjOF9XHUaDUuipryrarrhqc5k=; b=JIZv0vZlClHXgj7127g8+kz2SRAr0Px3UoYls6ptGkhWdbdq2YobumRaWhdMF90BjQSxlp eXwOfHeMmjmbjKXoX7xNNU7RaeiDHkSB6FrpfzvEPDyPkkC38h9m2xx7Bg2U7vQvBCj3tq bWXWe1kLdjto2uFwDP38VDeu9Vk92Qc= Date: Tue, 1 Jul 2025 12:20:37 -0400 MIME-Version: 1.0 Subject: Re: [PATCH net-next v2 10/18] net: macb: remove illusion about TBQPH/RBQPH being per-queue X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Sean Anderson To: =?UTF-8?Q?Th=C3=A9o_Lebrun?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Samuel Holland , Richard Cochran , Russell King , Thomas Bogendoerfer , Vladimir Kondratiev , Gregory CLEMENT , Cyrille Pitchen , Harini Katakam , Rafal Ozieblo , Haavard Skinnemoen , Jeff Garzik Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-mips@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk References: <20250627-macb-v2-0-ff8207d0bb77@bootlin.com> <20250627-macb-v2-10-ff8207d0bb77@bootlin.com> Content-Language: en-US In-Reply-To: X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250701_092049_494842_23E10591 X-CRM114-Status: GOOD ( 24.91 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gNy8xLzI1IDEyOjE1LCBTZWFuIEFuZGVyc29uIHdyb3RlOgo+IE9uIDYvMjcvMjUgMDU6MDgs IFRow6lvIExlYnJ1biB3cm90ZToKPj4gVGhlIE1BQ0IgZHJpdmVyIGFjdHMgYXMgaWYgVEJRUEgv UkJRUEggYXJlIGNvbmZpZ3VyYWJsZSBvbiBhIHBlciBxdWV1ZQo+PiBiYXNpczsgdGhpcyBpcyBh IGxpZS4gQSBzaW5nbGUgcmVnaXN0ZXIgY29uZmlndXJlcyB0aGUgdXBwZXIgMzIgYml0cyBvZgo+ PiBlYWNoIERNQSBkZXNjcmlwdG9yIGJ1ZmZlcnMgZm9yIGFsbCBxdWV1ZXMuCj4+IAo+PiBDb25j cmV0ZSBhY3Rpb25zOgo+PiAKPj4gIC0gRHJvcCBHRU1fVEJRUEgvR0VNX1JCUVBIIG1hY3JvcyB3 aGljaCBoYXZlIGEgcXVldWUgaW5kZXggYXJndW1lbnQuCj4+ICAgIE9ubHkgdXNlIE1BQ0JfVEJR UEgvTUFDQl9SQlFQSCBjb25zdGFudHMuCj4+IAo+PiAgLSBEcm9wIHN0cnVjdCBtYWNiX3F1ZXVl LT5UQlFQSC9SQlFQSCBmaWVsZHMuCj4+IAo+PiAgLSBJbiBtYWNiX2luaXRfYnVmZmVycygpOiBk byBhIHNpbmdsZSB3cml0ZSB0byBUQlFQSCBhbmQgUkJRUEggZm9yIGFsbAo+PiAgICBxdWV1ZXMg aW5zdGVhZCBvZiBhIHdyaXRlIHBlciBxdWV1ZS4KPj4gCj4+ICAtIEluIG1hY2JfdHhfZXJyb3Jf dGFzaygpOiBkcm9wIHRoZSB3cml0ZSB0byBUQlFQSC4KPj4gCj4+ICAtIEluIG1hY2JfYWxsb2Nf Y29uc2lzdGVudCgpOiBpZiBhbGxvY2F0aW9ucyBnaXZlIGRpZmZlcmVudCB1cHBlcgo+PiAgICAz Mi1iaXRzLCBmYWlsLiBQcmV2aW91c2x5LCBpdCB3b3VsZCBoYXZlIGxlYWQgdG8gc2lsZW50IG1l bW9yeQo+PiAgICBjb3JydXB0aW9uIGFzIHF1ZXVlcyB3b3VsZCBoYXZlIHVzZWQgdGhlIHVwcGVy IDMyIGJpdHMgb2YgdGhlIGFsbG9jCj4+ICAgIGZyb20gcXVldWUgMCBhbmQgdGhlaXIgb3duIGxv dyAzMiBiaXRzLgo+IAo+IFdoaWxlIGJldHRlciB0aGFuIHNpbGVudCBtZW1vcnkgY29ycnVwdGlv biwgdGhpcyBpcyBub3QgYSBnb29kIHNvbHV0aW9uCj4gc2luY2UgYnJpbmdpbmcgdGhlIG5ldGRl diB1cCB3aWxsIG5vdyByYW5kb21seSBmYWlsLiBDYW4gd2UgYWxsb2NhdGUgdGhlCj4gcmluZ3Mg aW4gb25lIGNvbnRpZ3VvdXMgY2h1bmsgaW5zdGVhZD8KCkFoLCBsb29rcyBsaWtlIHlvdSBkbyB0 aGlzIGluIHRoZSBuZXh0IHBhdGNoLiBJbiB0aGF0IGNhc2UsICh3aXRoIHRoZSBvdGhlcgpjb21t ZW50cyBhZGRyZXNzZWQpCgpSZXZpZXdlZC1ieTogU2VhbiBBbmRlcnNvbiA8c2Vhbi5hbmRlcnNv bkBsaW51eC5kZXY+Cgo+PiAgLSBJbiBtYWNiX3N1c3BlbmQoKTogaWYgd2UgdXNlIHRoZSB0aWUg b2ZmIGRlc2NyaXB0b3IgZm9yIHN1c3BlbmQsIGRvCj4+ICAgIHRoZSB3cml0ZSBvbmNlIGZvciBh bGwgcXVldWVzIGluc3RlYWQgb2Ygb25jZSBwZXIgcXVldWUuCj4+IAo+PiBGaXhlczogZmZmODAx OWEwOGI2ICgibmV0OiBtYWNiOiBBZGQgNjQgYml0IGFkZHJlc3Npbmcgc3VwcG9ydCBmb3IgR0VN IikKPj4gRml4ZXM6IGFlMWYyYTU2ZDI3MyAoIm5ldDogbWFjYjogQWRkZWQgc3VwcG9ydCBmb3Ig bWFueSBSWCBxdWV1ZXMiKQo+PiBTaWduZWQtb2ZmLWJ5OiBUaMOpbyBMZWJydW4gPHRoZW8ubGVi cnVuQGJvb3RsaW4uY29tPgo+IAo+IEFzIHRoaXMgaXMgYSBidWdmaXgsIGNhbiB5b3UgbW92ZSBp dCBiZWZvcmUgeW91ciBjbGVhbnVwIHBhdGNoZXM/IFRoaXMKPiB3aWxsIG1ha2UgaXQgZWFzaWVy IHRvIGJhY2twb3J0IHRvIHN0YWJsZSBrZXJuZWxzLgo+IAo+PiAtLS0KPj4gIGRyaXZlcnMvbmV0 L2V0aGVybmV0L2NhZGVuY2UvbWFjYi5oICAgICAgfCAgNCAtLS0tCj4+ICBkcml2ZXJzL25ldC9l dGhlcm5ldC9jYWRlbmNlL21hY2JfbWFpbi5jIHwgMzYgKysrKysrKysrKysrKy0tLS0tLS0tLS0t LS0tLS0tLS0KPj4gIDIgZmlsZXMgY2hhbmdlZCwgMTQgaW5zZXJ0aW9ucygrKSwgMjYgZGVsZXRp b25zKC0pCj4+IAo+PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9uZXQvZXRoZXJuZXQvY2FkZW5jZS9t YWNiLmggYi9kcml2ZXJzL25ldC9ldGhlcm5ldC9jYWRlbmNlL21hY2IuaAo+PiBpbmRleCA3MDdi MzI4NmE2Yjg0MDhhM2JjNGJiYmNiMTMzNWFlOGMzY2Q5NWFkLi5hZGM3MGI2ZWZkNTJiMGIxMWU0 MzZjMmM5NWJiNTEwOGM0MGYzNDkwIDEwMDY0NAo+PiAtLS0gYS9kcml2ZXJzL25ldC9ldGhlcm5l dC9jYWRlbmNlL21hY2IuaAo+PiArKysgYi9kcml2ZXJzL25ldC9ldGhlcm5ldC9jYWRlbmNlL21h Y2IuaAo+PiBAQCAtMjA5LDEwICsyMDksOCBAQAo+PiAgCj4+ICAjZGVmaW5lIEdFTV9JU1IoaHdf cSkJCSgweDA0MDAgKyAoKGh3X3EpIDw8IDIpKQo+PiAgI2RlZmluZSBHRU1fVEJRUChod19xKQkJ KDB4MDQ0MCArICgoaHdfcSkgPDwgMikpCj4+IC0jZGVmaW5lIEdFTV9UQlFQSChod19xKQkJKDB4 MDRDOCkKPj4gICNkZWZpbmUgR0VNX1JCUVAoaHdfcSkJCSgweDA0ODAgKyAoKGh3X3EpIDw8IDIp KQo+PiAgI2RlZmluZSBHRU1fUkJRUyhod19xKQkJKDB4MDRBMCArICgoaHdfcSkgPDwgMikpCj4+ IC0jZGVmaW5lIEdFTV9SQlFQSChod19xKQkJKDB4MDRENCkKPj4gICNkZWZpbmUgR0VNX0lFUiho d19xKQkJKDB4MDYwMCArICgoaHdfcSkgPDwgMikpCj4+ICAjZGVmaW5lIEdFTV9JRFIoaHdfcSkJ CSgweDA2MjAgKyAoKGh3X3EpIDw8IDIpKQo+PiAgI2RlZmluZSBHRU1fSU1SKGh3X3EpCQkoMHgw NjQwICsgKChod19xKSA8PCAyKSkKPj4gQEAgLTEyMDgsMTAgKzEyMDYsOCBAQCBzdHJ1Y3QgbWFj Yl9xdWV1ZSB7Cj4+ICAJdW5zaWduZWQgaW50CQlJRFI7Cj4+ICAJdW5zaWduZWQgaW50CQlJTVI7 Cj4+ICAJdW5zaWduZWQgaW50CQlUQlFQOwo+PiAtCXVuc2lnbmVkIGludAkJVEJRUEg7Cj4+ICAJ dW5zaWduZWQgaW50CQlSQlFTOwo+PiAgCXVuc2lnbmVkIGludAkJUkJRUDsKPj4gLQl1bnNpZ25l ZCBpbnQJCVJCUVBIOwo+PiAgCj4+ICAJLyogTG9jayB0byBwcm90ZWN0IHR4X2hlYWQgYW5kIHR4 X3RhaWwgKi8KPj4gIAlzcGlubG9ja190CQl0eF9wdHJfbG9jazsKPj4gZGlmZiAtLWdpdCBhL2Ry aXZlcnMvbmV0L2V0aGVybmV0L2NhZGVuY2UvbWFjYl9tYWluLmMgYi9kcml2ZXJzL25ldC9ldGhl cm5ldC9jYWRlbmNlL21hY2JfbWFpbi5jCj4+IGluZGV4IGE2NjMzZTA3NjY0NDA4OWM3OTY0NTNm ODU2YTc2NjI5OWJhZTJlYzYuLmQzYjM2MzU5OThjYWQwOTUyNDZlZGY4YTc1ZmFlYmJjZjcxMTUz NTUgMTAwNjQ0Cj4+IC0tLSBhL2RyaXZlcnMvbmV0L2V0aGVybmV0L2NhZGVuY2UvbWFjYl9tYWlu LmMKPj4gKysrIGIvZHJpdmVycy9uZXQvZXRoZXJuZXQvY2FkZW5jZS9tYWNiX21haW4uYwo+PiBA QCAtNDgyLDE1ICs0ODIsMTUgQEAgc3RhdGljIHZvaWQgbWFjYl9pbml0X2J1ZmZlcnMoc3RydWN0 IG1hY2IgKmJwKQo+PiAgCXN0cnVjdCBtYWNiX3F1ZXVlICpxdWV1ZTsKPj4gIAl1bnNpZ25lZCBp bnQgcTsKPj4gIAo+PiArCWlmIChtYWNiX2RtYV9pc182NGIoYnApKSB7Cj4+ICsJCS8qIFNpbmds ZSByZWdpc3RlciBmb3IgYWxsIHF1ZXVlcycgaGlnaCAzMiBiaXRzLiAqLwo+PiArCQltYWNiX3dy aXRlbChicCwgUkJRUEgsIHVwcGVyXzMyX2JpdHMoYnAtPnF1ZXVlcy0+cnhfcmluZ19kbWEpKTsK Pj4gKwkJbWFjYl93cml0ZWwoYnAsIFRCUVBILCB1cHBlcl8zMl9iaXRzKGJwLT5xdWV1ZXMtPnR4 X3JpbmdfZG1hKSk7Cj4+ICsJfQo+PiArCj4+ICAJZm9yIChxID0gMCwgcXVldWUgPSBicC0+cXVl dWVzOyBxIDwgYnAtPm51bV9xdWV1ZXM7ICsrcSwgKytxdWV1ZSkgewo+PiAgCQlxdWV1ZV93cml0 ZWwocXVldWUsIFJCUVAsIGxvd2VyXzMyX2JpdHMocXVldWUtPnJ4X3JpbmdfZG1hKSk7Cj4+IC0J CWlmIChtYWNiX2RtYV9pc182NGIoYnApKQo+PiAtCQkJcXVldWVfd3JpdGVsKHF1ZXVlLCBSQlFQ SCwKPj4gLQkJCQkgICAgIHVwcGVyXzMyX2JpdHMocXVldWUtPnJ4X3JpbmdfZG1hKSk7Cj4+ICAJ CXF1ZXVlX3dyaXRlbChxdWV1ZSwgVEJRUCwgbG93ZXJfMzJfYml0cyhxdWV1ZS0+dHhfcmluZ19k bWEpKTsKPj4gLQkJaWYgKG1hY2JfZG1hX2lzXzY0YihicCkpCj4+IC0JCQlxdWV1ZV93cml0ZWwo cXVldWUsIFRCUVBILAo+PiAtCQkJCSAgICAgdXBwZXJfMzJfYml0cyhxdWV1ZS0+dHhfcmluZ19k bWEpKTsKPj4gIAl9Cj4+ICB9Cj4+ICAKPj4gQEAgLTExNDUsOCArMTE0NSw2IEBAIHN0YXRpYyB2 b2lkIG1hY2JfdHhfZXJyb3JfdGFzayhzdHJ1Y3Qgd29ya19zdHJ1Y3QgKndvcmspCj4+ICAKPj4g IAkvKiBSZWluaXRpYWxpemUgdGhlIFRYIGRlc2MgcXVldWUgKi8KPj4gIAlxdWV1ZV93cml0ZWwo cXVldWUsIFRCUVAsIGxvd2VyXzMyX2JpdHMocXVldWUtPnR4X3JpbmdfZG1hKSk7Cj4+IC0JaWYg KG1hY2JfZG1hX2lzXzY0YihicCkpCj4+IC0JCXF1ZXVlX3dyaXRlbChxdWV1ZSwgVEJRUEgsIHVw cGVyXzMyX2JpdHMocXVldWUtPnR4X3JpbmdfZG1hKSk7Cj4+ICAJLyogTWFrZSBUWCByaW5nIHJl ZmxlY3Qgc3RhdGUgb2YgaGFyZHdhcmUgKi8KPj4gIAlxdWV1ZS0+dHhfaGVhZCA9IDA7Cj4+ICAJ cXVldWUtPnR4X3RhaWwgPSAwOwo+PiBAQCAtMjUyNCw3ICsyNTIyLDggQEAgc3RhdGljIGludCBt YWNiX2FsbG9jX2NvbnNpc3RlbnQoc3RydWN0IG1hY2IgKmJwKQo+PiAgCQlxdWV1ZS0+dHhfcmlu ZyA9IGRtYV9hbGxvY19jb2hlcmVudCgmYnAtPnBkZXYtPmRldiwgc2l6ZSwKPj4gIAkJCQkJCSAg ICAmcXVldWUtPnR4X3JpbmdfZG1hLAo+PiAgCQkJCQkJICAgIEdGUF9LRVJORUwpOwo+PiAtCQlp ZiAoIXF1ZXVlLT50eF9yaW5nKQo+PiArCQlpZiAoIXF1ZXVlLT50eF9yaW5nIHx8Cj4+ICsJCSAg ICB1cHBlcl8zMl9iaXRzKHF1ZXVlLT50eF9yaW5nX2RtYSkgIT0gdXBwZXJfMzJfYml0cyhicC0+ cXVldWVzLT50eF9yaW5nX2RtYSkpCj4+ICAJCQlnb3RvIG91dF9lcnI7Cj4+ICAJCW5ldGRldl9k YmcoYnAtPmRldiwKPj4gIAkJCSAgICJBbGxvY2F0ZWQgVFggcmluZyBmb3IgcXVldWUgJXUgb2Yg JWQgYnl0ZXMgYXQgJTA4bHggKG1hcHBlZCAlcClcbiIsCj4+IEBAIC0yNTM5LDcgKzI1MzgsOCBA QCBzdGF0aWMgaW50IG1hY2JfYWxsb2NfY29uc2lzdGVudChzdHJ1Y3QgbWFjYiAqYnApCj4+ICAJ CXNpemUgPSBSWF9SSU5HX0JZVEVTKGJwKSArIGJwLT5yeF9iZF9yZF9wcmVmZXRjaDsKPj4gIAkJ cXVldWUtPnJ4X3JpbmcgPSBkbWFfYWxsb2NfY29oZXJlbnQoJmJwLT5wZGV2LT5kZXYsIHNpemUs Cj4+ICAJCQkJCQkgJnF1ZXVlLT5yeF9yaW5nX2RtYSwgR0ZQX0tFUk5FTCk7Cj4+IC0JCWlmICgh cXVldWUtPnJ4X3JpbmcpCj4+ICsJCWlmICghcXVldWUtPnJ4X3JpbmcgfHwKPj4gKwkJICAgIHVw cGVyXzMyX2JpdHMocXVldWUtPnJ4X3JpbmdfZG1hKSAhPSB1cHBlcl8zMl9iaXRzKGJwLT5xdWV1 ZXMtPnJ4X3JpbmdfZG1hKSkKPiAKPiBDYW4geW91IHdyaXRlIHRoaXMgYXMgYnAtPnF1ZXVlc1sw XS5yeF9yaW5nX2RtYSBmb3IgY2xhcml0eT8KPiAKPj4gIAkJCWdvdG8gb3V0X2VycjsKPj4gIAkJ bmV0ZGV2X2RiZyhicC0+ZGV2LAo+PiAgCQkJICAgIkFsbG9jYXRlZCBSWCByaW5nIG9mICVkIGJ5 dGVzIGF0ICUwOGx4IChtYXBwZWQgJXApXG4iLAo+PiBAQCAtNDI2OSwxMCArNDI2OSw2IEBAIHN0 YXRpYyBpbnQgbWFjYl9pbml0KHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpCj4+ICAJCQlx dWV1ZS0+VEJRUCA9IEdFTV9UQlFQKGh3X3EgLSAxKTsKPj4gIAkJCXF1ZXVlLT5SQlFQID0gR0VN X1JCUVAoaHdfcSAtIDEpOwo+PiAgCQkJcXVldWUtPlJCUVMgPSBHRU1fUkJRUyhod19xIC0gMSk7 Cj4+IC0JCQlpZiAobWFjYl9kbWFfaXNfNjRiKGJwKSkgewo+PiAtCQkJCXF1ZXVlLT5UQlFQSCA9 IEdFTV9UQlFQSChod19xIC0gMSk7Cj4+IC0JCQkJcXVldWUtPlJCUVBIID0gR0VNX1JCUVBIKGh3 X3EgLSAxKTsKPj4gLQkJCX0KPj4gIAkJfSBlbHNlIHsKPj4gIAkJCS8qIHF1ZXVlMCB1c2VzIGxl Z2FjeSByZWdpc3RlcnMgKi8KPj4gIAkJCXF1ZXVlLT5JU1IgID0gTUFDQl9JU1I7Cj4+IEBAIC00 MjgxLDEwICs0Mjc3LDYgQEAgc3RhdGljIGludCBtYWNiX2luaXQoc3RydWN0IHBsYXRmb3JtX2Rl dmljZSAqcGRldikKPj4gIAkJCXF1ZXVlLT5JTVIgID0gTUFDQl9JTVI7Cj4+ICAJCQlxdWV1ZS0+ VEJRUCA9IE1BQ0JfVEJRUDsKPj4gIAkJCXF1ZXVlLT5SQlFQID0gTUFDQl9SQlFQOwo+PiAtCQkJ aWYgKG1hY2JfZG1hX2lzXzY0YihicCkpIHsKPj4gLQkJCQlxdWV1ZS0+VEJRUEggPSBNQUNCX1RC UVBIOwo+PiAtCQkJCXF1ZXVlLT5SQlFQSCA9IE1BQ0JfUkJRUEg7Cj4+IC0JCQl9Cj4+ICAJCX0K Pj4gIAo+PiAgCQkvKiBnZXQgaXJxOiBoZXJlIHdlIHVzZSB0aGUgbGludXggcXVldWUgaW5kZXgs IG5vdCB0aGUgaGFyZHdhcmUKPj4gQEAgLTU0MDEsNiArNTM5MywxMCBAQCBzdGF0aWMgaW50IF9f bWF5YmVfdW51c2VkIG1hY2Jfc3VzcGVuZChzdHJ1Y3QgZGV2aWNlICpkZXYpCj4+ICAJCSAqLwo+ PiAgCQl0bXAgPSBtYWNiX3JlYWRsKGJwLCBOQ1IpOwo+PiAgCQltYWNiX3dyaXRlbChicCwgTkNS LCB0bXAgJiB+KE1BQ0JfQklUKFRFKSB8IE1BQ0JfQklUKFJFKSkpOwo+PiArI2lmZGVmIENPTkZJ R19BUkNIX0RNQV9BRERSX1RfNjRCSVQKPj4gKwkJaWYgKCEoYnAtPmNhcHMgJiBNQUNCX0NBUFNf UVVFVUVfRElTQUJMRSkpCj4+ICsJCQltYWNiX3dyaXRlbChicCwgUkJRUEgsIHVwcGVyXzMyX2Jp dHMoYnAtPnJ4X3JpbmdfdGllb2ZmX2RtYSkpOwo+PiArI2VuZGlmCj4+ICAJCWZvciAocSA9IDAs IHF1ZXVlID0gYnAtPnF1ZXVlczsgcSA8IGJwLT5udW1fcXVldWVzOwo+PiAgCQkgICAgICsrcSwg KytxdWV1ZSkgewo+PiAgCQkJLyogRGlzYWJsZSBSWCBxdWV1ZXMgKi8KPj4gQEAgLTU0MTAsMTAg KzU0MDYsNiBAQCBzdGF0aWMgaW50IF9fbWF5YmVfdW51c2VkIG1hY2Jfc3VzcGVuZChzdHJ1Y3Qg ZGV2aWNlICpkZXYpCj4+ICAJCQkJLyogVGllIG9mZiBSWCBxdWV1ZXMgKi8KPj4gIAkJCQlxdWV1 ZV93cml0ZWwocXVldWUsIFJCUVAsCj4+ICAJCQkJCSAgICAgbG93ZXJfMzJfYml0cyhicC0+cnhf cmluZ190aWVvZmZfZG1hKSk7Cj4+IC0jaWZkZWYgQ09ORklHX0FSQ0hfRE1BX0FERFJfVF82NEJJ VAo+PiAtCQkJCXF1ZXVlX3dyaXRlbChxdWV1ZSwgUkJRUEgsCj4+IC0JCQkJCSAgICAgdXBwZXJf MzJfYml0cyhicC0+cnhfcmluZ190aWVvZmZfZG1hKSk7Cj4+IC0jZW5kaWYKPj4gIAkJCX0KPj4g IAkJCS8qIERpc2FibGUgYWxsIGludGVycnVwdHMgKi8KPj4gIAkJCXF1ZXVlX3dyaXRlbChxdWV1 ZSwgSURSLCAtMSk7Cj4+IAoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fCmxpbnV4LXJpc2N2IG1haWxpbmcgbGlzdApsaW51eC1yaXNjdkBsaXN0cy5pbmZy YWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGlu dXgtcmlzY3YK