From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F760C26E for ; Thu, 9 Mar 2023 18:24:32 +0000 (UTC) Received: from lhrpeml100003.china.huawei.com (unknown [172.18.147.226]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4PXcyr3Yg1z6J7f5; Fri, 10 Mar 2023 02:24:20 +0800 (CST) Received: from lhrpeml500005.china.huawei.com (7.191.163.240) by lhrpeml100003.china.huawei.com (7.191.160.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 9 Mar 2023 18:24:29 +0000 Received: from lhrpeml500005.china.huawei.com ([7.191.163.240]) by lhrpeml500005.china.huawei.com ([7.191.163.240]) with mapi id 15.01.2507.021; Thu, 9 Mar 2023 18:24:29 +0000 From: Shameerali Kolothum Thodi To: Robin Murphy , Nicolin Chen , "jgg@nvidia.com" , "will@kernel.org" CC: "eric.auger@redhat.com" , "kevin.tian@intel.com" , "baolu.lu@linux.intel.com" , "joro@8bytes.org" , "jean-philippe@linaro.org" , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH v1 06/14] iommu/arm-smmu-v3: Unset corresponding STE fields when s2_cfg is NULL Thread-Topic: [PATCH v1 06/14] iommu/arm-smmu-v3: Unset corresponding STE fields when s2_cfg is NULL Thread-Index: AQHZUnWW/wX8VWz+vEGpoiDFTSTiqa7ybOCAgABO2MA= Date: Thu, 9 Mar 2023 18:24:29 +0000 Message-ID: References: <995e48fe6eb9e31c71dbe8bb80d445aa34a51819.1678348754.git.nicolinc@nvidia.com> <4e426dc4-6852-336f-7321-5b4df69fd430@arm.com> In-Reply-To: <4e426dc4-6852-336f-7321-5b4df69fd430@arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.227.178] Content-Type: text/plain; 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Thu, 09 Mar 2023 18:24:41 +0000 Received: from frasgout.his.huawei.com ([185.176.79.56]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1paKwO-00BXtR-ST for linux-arm-kernel@lists.infradead.org; Thu, 09 Mar 2023 18:24:39 +0000 Received: from lhrpeml100003.china.huawei.com (unknown [172.18.147.226]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4PXcyr3Yg1z6J7f5; Fri, 10 Mar 2023 02:24:20 +0800 (CST) Received: from lhrpeml500005.china.huawei.com (7.191.163.240) by lhrpeml100003.china.huawei.com (7.191.160.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 9 Mar 2023 18:24:29 +0000 Received: from lhrpeml500005.china.huawei.com ([7.191.163.240]) by lhrpeml500005.china.huawei.com ([7.191.163.240]) with mapi id 15.01.2507.021; Thu, 9 Mar 2023 18:24:29 +0000 From: Shameerali Kolothum Thodi To: Robin Murphy , Nicolin Chen , "jgg@nvidia.com" , "will@kernel.org" CC: "eric.auger@redhat.com" , "kevin.tian@intel.com" , "baolu.lu@linux.intel.com" , "joro@8bytes.org" , "jean-philippe@linaro.org" , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH v1 06/14] iommu/arm-smmu-v3: Unset corresponding STE fields when s2_cfg is NULL Thread-Topic: [PATCH v1 06/14] iommu/arm-smmu-v3: Unset corresponding STE fields when s2_cfg is NULL Thread-Index: AQHZUnWW/wX8VWz+vEGpoiDFTSTiqa7ybOCAgABO2MA= Date: Thu, 9 Mar 2023 18:24:29 +0000 Message-ID: References: <995e48fe6eb9e31c71dbe8bb80d445aa34a51819.1678348754.git.nicolinc@nvidia.com> <4e426dc4-6852-336f-7321-5b4df69fd430@arm.com> In-Reply-To: <4e426dc4-6852-336f-7321-5b4df69fd430@arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.227.178] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230309_102437_248001_B1E73FDA X-CRM114-Status: GOOD ( 17.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Robin Murphy [mailto:robin.murphy@arm.com] > Sent: 09 March 2023 13:13 > To: Nicolin Chen ; jgg@nvidia.com; will@kernel.org > Cc: eric.auger@redhat.com; kevin.tian@intel.com; baolu.lu@linux.intel.com; > joro@8bytes.org; Shameerali Kolothum Thodi > ; jean-philippe@linaro.org; > linux-arm-kernel@lists.infradead.org; iommu@lists.linux.dev; > linux-kernel@vger.kernel.org > Subject: Re: [PATCH v1 06/14] iommu/arm-smmu-v3: Unset corresponding > STE fields when s2_cfg is NULL > > On 2023-03-09 10:53, Nicolin Chen wrote: > > From: Eric Auger > > > > Despite the spec does not seem to mention this, on some implementations, > > when the STE configuration switches from an S1+S2 cfg to an S1 only one, > > a C_BAD_STE error would happen if dst[3] (S2TTB) is not reset. > > Can you provide more details, since it's not clear whether this is a > hardware erratum workaround or a bodge around the driver itself doing > something wrong like not doing a proper break-before-make transition of > the STE. The architecture explicitly states that all the STE.S2* fields > except S2VMID and potentially S2S are ignored when Stage 2 is bypassed. Took a while to locate the email thread where this was discussed, https://patchwork.kernel.org/cover/11449895/#23244457 This was observed on a HiSilicon implementation where, if the SMMUv3 is configured with both Stage 1 and Stage 2 (nested) mode once, then it is not possible to configure it back for Stage 1 mode for the same device(stream id). IIRC, the SMMUv3 implementation on these boards expects to set the S2TTB field in STE to zero when using S1, otherwise it reports C_BAD_STE error. :( You are right that the specification doesn't demand this and I am not sure there are any other Hardware that requires this. Could we please have this with a comment added in the code? Thanks, Shameer _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel