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([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id m63-20020a625842000000b006bdd1ce6915sm36435pfb.193.2023.11.16.10.32.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Nov 2023 10:32:58 -0800 (PST) Message-ID: Date: Thu, 16 Nov 2023 15:32:54 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] Fix SiFive E CLINT clock frequency (#1978) Content-Language: en-US To: =?UTF-8?Q?Rom=C3=A1n_C=C3=A1rdenas?= , qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Alistair.Francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, qemu-riscv@nongnu.org References: <20231116120702.53170-1-rcardenas.rod@gmail.com> From: Daniel Henrique Barboza In-Reply-To: <20231116120702.53170-1-rcardenas.rod@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-trivial@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Nov 2023 18:33:03 -0000 I believe you forgot to add your Signed-off-by tag. Without it we can't accept the patch hehe Since you'll need to send another version with the S-o-b, please change the commit title to "riscv: Fix SiFive E CLINT clock frequency" That way other people will quickly identify which sub-tree this patch belongs. The Gitlab bug number you put it in the end of the commit msg in a tag: On 11/16/23 09:07, Román Cárdenas wrote: > If you check the manual of SiFive E310 (https://cdn.sparkfun.com/assets/7/f/0/2/7/fe310-g002-manual-v19p05.pdf?_gl=1*w2ieef*_ga*MTcyNDI2MjM0Ny4xNjk2ODcwNTM3*_ga_T369JS7J9N*MTY5Njg3MDUzNy4xLjAuMTY5Njg3MDUzNy42MC4wLjA.), you can see in Figure 1 that the CLINT is connected to the real time clock, which also feeds the AON peripheral (they share the same clock). > > In page 43, the docs also say that the timer registers of the CLINT count ticks from the rtcclk. > > I am currently playing with bare metal applications both in QEMU and a physical SiFive E310 board and I confirm that the CLINT clock in the physical board runs at 32.768 kHz. In QEMU, the same app produces a completely different outcome, as sometimes a new CLINT interrupt is triggered before finishing other tasks. > > You can check issue #1978 on GitLab for more information. > Like this: Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1978 The rest of the commit msg and the code looks good to me. Thanks, Daniel > --- > hw/riscv/sifive_e.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index 0d37adc542..87d9602383 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -225,7 +225,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp) > RISCV_ACLINT_SWI_SIZE, > RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, > RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, > - RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); > + SIFIVE_E_LFCLK_DEFAULT_FREQ, false); > sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); > > /* AON */