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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4775592eeaasm49683145e9.3.2025.11.05.09.32.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Nov 2025 09:32:42 -0800 (PST) Message-ID: Date: Wed, 5 Nov 2025 18:32:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 15/32] hw/pci/pci: Introduce optional get_msi_address_space() callback To: Jason Gunthorpe , Nicolin Chen Cc: Shameer Kolothum , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , "ddutile@redhat.com" , "berrange@redhat.com" , Nathan Chen , Matt Ochs , "smostafa@google.com" , "wangzhou1@hisilicon.com" , "jiangkunkun@huawei.com" , "jonathan.cameron@huawei.com" , "zhangfei.gao@linaro.org" , "zhenzhong.duan@intel.com" , "yi.l.liu@intel.com" , Krishnakant Jaju References: <20251031105005.24618-16-skolothumtho@nvidia.com> <318947de-4467-4ced-a5d2-929e3df210ef@redhat.com> <20251104142052.GD1537560@nvidia.com> <20251104145157.GF1537560@nvidia.com> <20251104151234.GG1537560@nvidia.com> <20251104153535.GH1537560@nvidia.com> <20251104174152.GI1537560@nvidia.com> From: Eric Auger In-Reply-To: <20251104174152.GI1537560@nvidia.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: lT4LSsVLBnyR2Sp4OOwfLU2nS8T-320HRRK6al3CqpE_1762363964 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.517, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 11/4/25 6:41 PM, Jason Gunthorpe wrote: > On Tue, Nov 04, 2025 at 09:11:55AM -0800, Nicolin Chen wrote: >> On Tue, Nov 04, 2025 at 11:35:35AM -0400, Jason Gunthorpe wrote: >>> On Tue, Nov 04, 2025 at 03:20:59PM +0000, Shameer Kolothum wrote: >>>>> On Tue, Nov 04, 2025 at 02:58:44PM +0000, Shameer Kolothum wrote: >>>>>>> Sure it is trapped, but nothing should be looking at the MSI address >>>>>>> from the guest, it is meaningless and wrong information. Just ignore >>>>>>> it. >>>>>> Hmm.. we need to setup the doorbell address correctly. >>>>>> If we don't do the translation here, it will use the Guest IOVA >>>>>> address. Remember, we are using the IORT RMR identity mapping to get >>>>>> MSI working. >>>>> Either you use the RMR value, which is forced by the kernel into the >>>>> physical MSI through iommufd and kernel ignores anything qemu >>>>> does. So fully ignore the guest's vMSI address. >>>> Well, we are sort of trying to do the same through this patch here. >>>> But to avoid a "translation" completely it will involve some changes to >>>> Qemu pci subsystem. I think this is the least intrusive path I can think >>>> of now. And this is a one time setup mostly. >>> Should be explained in the commit message that the translation is >>> pointless. I'm not sure about this, any translation seems risky >>> because it could fail. The guest can use any IOVA for MSI and none may >>> fail. in general the translation is not pointless (I mean when RMR are not applied). In case a vhost device (virtio-net) for instance is protected by SMMU, vhost triggers irqfds upon which a gsi is injected in vgic. This latter does irq_routing mapping and this gsi is associated to an MSI address/data. If the MSI address is wrong, ie. not corresponding to the vITS gpa doorbell, kernel kvm/vgic/vgic-its.c vgic_its_trigger_msi will fail to inject the MSI on guest since vgic_msi_to_its/__vgic_doorbell_to_its will fail to find the ITS instance to inject in. Thanks Eric >> In the current design of KVM in QEMU, it does a generic translation >> from gIOVA->gPA for the doorbell location to inject IRQ, whether VM >> has an accelerated IOMMU or an emulated IOMMU. > And what happens if the translation fails because there is no mapping? > It should be ignored for this case and not ignored for others. > > Jason >