diff for duplicates of <e9e3a16e28dc4aee72fb1b85b87ef612@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index c3afb76..745ceb7 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,5 +1,5 @@ On 2018-01-17 02:28, Suzuki K Poulose wrote: -> On 17/01/18 03:34, ckadabi at codeaurora.org wrote: +> On 17/01/18 03:34, ckadabi@codeaurora.org wrote: >> On 2018-01-16 02:23, Suzuki K Poulose wrote: >>> Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer >>> from an erratum 1024718, which causes incorrect updates when DBM/AP @@ -24,10 +24,10 @@ On 2018-01-17 02:28, Suzuki K Poulose wrote: >>> Cc: Will Deacon <will.deacon@arm.com> >>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> >>> --- ->>> ?Documentation/arm64/silicon-errata.txt |? 1 + ->>> ?arch/arm64/Kconfig???????????????????? | 14 ++++++++++++++ ->>> ?arch/arm64/mm/proc.S?????????????????? |? 5 +++++ ->>> ?3 files changed, 20 insertions(+) +>>> Documentation/arm64/silicon-errata.txt | 1 + +>>> arch/arm64/Kconfig | 14 ++++++++++++++ +>>> arch/arm64/mm/proc.S | 5 +++++ +>>> 3 files changed, 20 insertions(+) >>> >>> diff --git a/Documentation/arm64/silicon-errata.txt >>> b/Documentation/arm64/silicon-errata.txt @@ -35,62 +35,62 @@ On 2018-01-17 02:28, Suzuki K Poulose wrote: >>> --- a/Documentation/arm64/silicon-errata.txt >>> +++ b/Documentation/arm64/silicon-errata.txt >>> @@ -55,6 +55,7 @@ stable kernels. ->>> ?| ARM??????????? | Cortex-A57????? | #834220???????? | ->>> ARM64_ERRATUM_834220??????? | ->>> ?| ARM??????????? | Cortex-A72????? | #853709???????? | N/A ->>> ???????????? | ->>> ?| ARM??????????? | Cortex-A73????? | #858921???????? | ->>> ARM64_ERRATUM_858921??????? | ->>> +| ARM??????????? | Cortex-A55????? | #1024718??????? | ->>> ARM64_ERRATUM_1024718?????? | ->>> ?| ARM??????????? | MMU-500???????? | #841119,#826419 | N/A ->>> ???????????? | ->>> ?|??????????????? |???????????????? |???????????????? | ->>> ???????????? | ->>> ?| Cavium???????? | ThunderX ITS??? | #22375, #24313? | ->>> CAVIUM_ERRATUM_22375??????? | +>>> | ARM | Cortex-A57 | #834220 | +>>> ARM64_ERRATUM_834220 | +>>> | ARM | Cortex-A72 | #853709 | N/A +>>> | +>>> | ARM | Cortex-A73 | #858921 | +>>> ARM64_ERRATUM_858921 | +>>> +| ARM | Cortex-A55 | #1024718 | +>>> ARM64_ERRATUM_1024718 | +>>> | ARM | MMU-500 | #841119,#826419 | N/A +>>> | +>>> | | | | +>>> | +>>> | Cavium | ThunderX ITS | #22375, #24313 | +>>> CAVIUM_ERRATUM_22375 | >>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >>> index 664fadc2aa2e..19b8407a0325 100644 >>> --- a/arch/arm64/Kconfig >>> +++ b/arch/arm64/Kconfig >>> @@ -461,6 +461,20 @@ config ARM64_ERRATUM_843419 >>> ->>> ?????? If unsure, say Y. +>>> If unsure, say Y. >>> >>> +config ARM64_ERRATUM_1024718 ->>> +??? bool "Cortex-A55: 1024718: Update of DBM/AP bits without break +>>> + bool "Cortex-A55: 1024718: Update of DBM/AP bits without break >>> before make might result in incorrect update" ->>> +??? default y ->>> +??? help ->>> +????? This option adds work around for Arm Cortex-A55 Erratum +>>> + default y +>>> + help +>>> + This option adds work around for Arm Cortex-A55 Erratum >>> 1024718. >>> + ->>> +????? Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause +>>> + Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause >>> incorrect ->>> +????? update of the hardware dirty bit when the DBM/AP bits are +>>> + update of the hardware dirty bit when the DBM/AP bits are >>> updated ->>> +????? without a break-before-make. The work around is to disable the +>>> + without a break-before-make. The work around is to disable the >>> usage ->>> +????? of hardware DBM locally on the affected cores. CPUs not +>>> + of hardware DBM locally on the affected cores. CPUs not >>> affected by ->>> +????? erratum will continue to use the feature. +>>> + erratum will continue to use the feature. >>> + ->>> +????? If unsure, say Y. +>>> + If unsure, say Y. >>> + ->>> ?config CAVIUM_ERRATUM_22375 ->>> ???? bool "Cavium erratum 22375, 24313" ->>> ???? default y +>>> config CAVIUM_ERRATUM_22375 +>>> bool "Cavium erratum 22375, 24313" +>>> default y >>> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S >>> index 5a59eea49395..ba2c22180f4e 100644 >>> --- a/arch/arm64/mm/proc.S >>> +++ b/arch/arm64/mm/proc.S >>> @@ -252,6 +252,11 @@ ENTRY(__cpu_setup) ->>> ???? cbz??? x9, 2f ->>> ???? cmp??? x9, #2 ->>> ???? b.lt??? 1f +>>> cbz x9, 2f +>>> cmp x9, #2 +>>> b.lt 1f >>> +#ifdef CONFIG_ARM64_ERRATUM_1024718 ->>> +??? /* Disable hardware DBM on Cortex-A55 r0p0, r0p1 & r1p0 */ ->>> +??? cpu_midr_match MIDR_CORTEX_A55, MIDR_CPU_VAR_REV(0, 0), +>>> + /* Disable hardware DBM on Cortex-A55 r0p0, r0p1 & r1p0 */ +>>> + cpu_midr_match MIDR_CORTEX_A55, MIDR_CPU_VAR_REV(0, 0), >> >> What is there is a custom core with different MIDRs, can we specify >> multiple MIDR values? diff --git a/a/content_digest b/N1/content_digest index 6cc6fd9..80e5dc5 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,14 +2,21 @@ "ref\020180116102323.3470-4-suzuki.poulose@arm.com\0" "ref\05bff2bc7fc3d5d04d8fccc099599dd58@codeaurora.org\0" "ref\04b06ad53-e8a6-abd2-2ecf-177abb71bdfe@arm.com\0" - "From\0ckadabi@codeaurora.org (Channa)\0" - "Subject\0[PATCH 3/3] arm64: Add work around for Arm Cortex-A55 Erratum 1024718\0" + "From\0Channa <ckadabi@codeaurora.org>\0" + "Subject\0Re: [PATCH 3/3] arm64: Add work around for Arm Cortex-A55 Erratum 1024718\0" "Date\0Wed, 17 Jan 2018 21:00:38 -0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Suzuki K Poulose <Suzuki.Poulose@arm.com>\0" + "Cc\0linux-arm-kernel@lists.infradead.org" + linux-kernel@vger.kernel.org + catalin.marinas@arm.com + mark.rutland@arm.com + will.deacon@arm.com + marc.zyngier@arm.com + " linux-kernel-owner@vger.kernel.org\0" "\00:1\0" "b\0" "On 2018-01-17 02:28, Suzuki K Poulose wrote:\n" - "> On 17/01/18 03:34, ckadabi at codeaurora.org wrote:\n" + "> On 17/01/18 03:34, ckadabi@codeaurora.org wrote:\n" ">> On 2018-01-16 02:23, Suzuki K Poulose wrote:\n" ">>> Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer\n" ">>> from an erratum 1024718, which causes incorrect updates when DBM/AP\n" @@ -34,10 +41,10 @@ ">>> Cc: Will Deacon <will.deacon@arm.com>\n" ">>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>\n" ">>> ---\n" - ">>> ?Documentation/arm64/silicon-errata.txt |? 1 +\n" - ">>> ?arch/arm64/Kconfig???????????????????? | 14 ++++++++++++++\n" - ">>> ?arch/arm64/mm/proc.S?????????????????? |? 5 +++++\n" - ">>> ?3 files changed, 20 insertions(+)\n" + ">>> \302\240Documentation/arm64/silicon-errata.txt |\302\240 1 +\n" + ">>> \302\240arch/arm64/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 | 14 ++++++++++++++\n" + ">>> \302\240arch/arm64/mm/proc.S\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240 5 +++++\n" + ">>> \302\2403 files changed, 20 insertions(+)\n" ">>> \n" ">>> diff --git a/Documentation/arm64/silicon-errata.txt\n" ">>> b/Documentation/arm64/silicon-errata.txt\n" @@ -45,62 +52,62 @@ ">>> --- a/Documentation/arm64/silicon-errata.txt\n" ">>> +++ b/Documentation/arm64/silicon-errata.txt\n" ">>> @@ -55,6 +55,7 @@ stable kernels.\n" - ">>> ?| ARM??????????? | Cortex-A57????? | #834220???????? |\n" - ">>> ARM64_ERRATUM_834220??????? |\n" - ">>> ?| ARM??????????? | Cortex-A72????? | #853709???????? | N/A\n" - ">>> ???????????? |\n" - ">>> ?| ARM??????????? | Cortex-A73????? | #858921???????? |\n" - ">>> ARM64_ERRATUM_858921??????? |\n" - ">>> +| ARM??????????? | Cortex-A55????? | #1024718??????? |\n" - ">>> ARM64_ERRATUM_1024718?????? |\n" - ">>> ?| ARM??????????? | MMU-500???????? | #841119,#826419 | N/A\n" - ">>> ???????????? |\n" - ">>> ?|??????????????? |???????????????? |???????????????? |\n" - ">>> ???????????? |\n" - ">>> ?| Cavium???????? | ThunderX ITS??? | #22375, #24313? |\n" - ">>> CAVIUM_ERRATUM_22375??????? |\n" + ">>> \302\240| ARM\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 | Cortex-A57\302\240\302\240\302\240\302\240\302\240 | #834220\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\n" + ">>> ARM64_ERRATUM_834220\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\n" + ">>> \302\240| ARM\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 | Cortex-A72\302\240\302\240\302\240\302\240\302\240 | #853709\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 | N/A\n" + ">>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\n" + ">>> \302\240| ARM\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 | Cortex-A73\302\240\302\240\302\240\302\240\302\240 | #858921\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\n" + ">>> ARM64_ERRATUM_858921\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\n" + ">>> +| ARM\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 | Cortex-A55\302\240\302\240\302\240\302\240\302\240 | #1024718\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\n" + ">>> ARM64_ERRATUM_1024718\302\240\302\240\302\240\302\240\302\240\302\240 |\n" + ">>> \302\240| ARM\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 | MMU-500\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 | #841119,#826419 | N/A\n" + ">>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\n" + ">>> \302\240|\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\n" + ">>> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\n" + ">>> \302\240| Cavium\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 | ThunderX ITS\302\240\302\240\302\240 | #22375, #24313\302\240 |\n" + ">>> CAVIUM_ERRATUM_22375\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\n" ">>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig\n" ">>> index 664fadc2aa2e..19b8407a0325 100644\n" ">>> --- a/arch/arm64/Kconfig\n" ">>> +++ b/arch/arm64/Kconfig\n" ">>> @@ -461,6 +461,20 @@ config ARM64_ERRATUM_843419\n" ">>> \n" - ">>> ?????? If unsure, say Y.\n" + ">>> \302\240\302\240\302\240\302\240\302\240\302\240 If unsure, say Y.\n" ">>> \n" ">>> +config ARM64_ERRATUM_1024718\n" - ">>> +??? bool \"Cortex-A55: 1024718: Update of DBM/AP bits without break\n" + ">>> +\302\240\302\240\302\240 bool \"Cortex-A55: 1024718: Update of DBM/AP bits without break\n" ">>> before make might result in incorrect update\"\n" - ">>> +??? default y\n" - ">>> +??? help\n" - ">>> +????? This option adds work around for Arm Cortex-A55 Erratum \n" + ">>> +\302\240\302\240\302\240 default y\n" + ">>> +\302\240\302\240\302\240 help\n" + ">>> +\302\240\302\240\302\240\302\240\302\240 This option adds work around for Arm Cortex-A55 Erratum \n" ">>> 1024718.\n" ">>> +\n" - ">>> +????? Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause \n" + ">>> +\302\240\302\240\302\240\302\240\302\240 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause \n" ">>> incorrect\n" - ">>> +????? update of the hardware dirty bit when the DBM/AP bits are \n" + ">>> +\302\240\302\240\302\240\302\240\302\240 update of the hardware dirty bit when the DBM/AP bits are \n" ">>> updated\n" - ">>> +????? without a break-before-make. The work around is to disable the \n" + ">>> +\302\240\302\240\302\240\302\240\302\240 without a break-before-make. The work around is to disable the \n" ">>> usage\n" - ">>> +????? of hardware DBM locally on the affected cores. CPUs not \n" + ">>> +\302\240\302\240\302\240\302\240\302\240 of hardware DBM locally on the affected cores. CPUs not \n" ">>> affected by\n" - ">>> +????? erratum will continue to use the feature.\n" + ">>> +\302\240\302\240\302\240\302\240\302\240 erratum will continue to use the feature.\n" ">>> +\n" - ">>> +????? If unsure, say Y.\n" + ">>> +\302\240\302\240\302\240\302\240\302\240 If unsure, say Y.\n" ">>> +\n" - ">>> ?config CAVIUM_ERRATUM_22375\n" - ">>> ???? bool \"Cavium erratum 22375, 24313\"\n" - ">>> ???? default y\n" + ">>> \302\240config CAVIUM_ERRATUM_22375\n" + ">>> \302\240\302\240\302\240\302\240 bool \"Cavium erratum 22375, 24313\"\n" + ">>> \302\240\302\240\302\240\302\240 default y\n" ">>> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S\n" ">>> index 5a59eea49395..ba2c22180f4e 100644\n" ">>> --- a/arch/arm64/mm/proc.S\n" ">>> +++ b/arch/arm64/mm/proc.S\n" ">>> @@ -252,6 +252,11 @@ ENTRY(__cpu_setup)\n" - ">>> ???? cbz??? x9, 2f\n" - ">>> ???? cmp??? x9, #2\n" - ">>> ???? b.lt??? 1f\n" + ">>> \302\240\302\240\302\240\302\240 cbz\302\240\302\240\302\240 x9, 2f\n" + ">>> \302\240\302\240\302\240\302\240 cmp\302\240\302\240\302\240 x9, #2\n" + ">>> \302\240\302\240\302\240\302\240 b.lt\302\240\302\240\302\240 1f\n" ">>> +#ifdef CONFIG_ARM64_ERRATUM_1024718\n" - ">>> +??? /* Disable hardware DBM on Cortex-A55 r0p0, r0p1 & r1p0 */\n" - ">>> +??? cpu_midr_match MIDR_CORTEX_A55, MIDR_CPU_VAR_REV(0, 0),\n" + ">>> +\302\240\302\240\302\240 /* Disable hardware DBM on Cortex-A55 r0p0, r0p1 & r1p0 */\n" + ">>> +\302\240\302\240\302\240 cpu_midr_match MIDR_CORTEX_A55, MIDR_CPU_VAR_REV(0, 0),\n" ">> \n" ">> What is there is a custom core with different MIDRs, can we specify \n" ">> multiple MIDR values?\n" @@ -157,4 +164,4 @@ "Forum,\n" a Linux Foundation Collaborative Project -ac340309807da5d658e2dbe6d36ad356f15d4b5e717da1d3cc4a00ef200b2487 +5b1fdd44542170e242fb68b3ec8aeed2161214b7101197c7e3f07232dbd7c8cd
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.