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envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/15/2026 3:49 AM, Sunil V L wrote: > Generate the Processor Properties Topology Table (PPTT) for the RISC-V > virt machine. > > Describe the machine using separate L1 data and instruction caches plus > unified L2 and L3 caches, and enable the corresponding cache and cluster > SMP properties. > > Signed-off-by: Sunil V L > Signed-off-by: Sia Jee Heng > --- Reviewed-by: Daniel Henrique Barboza > hw/riscv/virt-acpi-build.c | 7 ++++++ > hw/riscv/virt.c | 51 ++++++++++++++++++++++++++++++++++++++ > include/hw/riscv/virt.h | 4 +++ > 3 files changed, 62 insertions(+) > > diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c > index 0475dcb5c601..8254f1294a72 100644 > --- a/hw/riscv/virt-acpi-build.c > +++ b/hw/riscv/virt-acpi-build.c > @@ -882,7 +882,10 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) > unsigned dsdt, xsdt; > GArray *tables_blob = tables->table_data; > MachineState *ms = MACHINE(s); > + CPUCoreCaches caches[CPU_MAX_CACHES]; > + unsigned int num_caches; > > + num_caches = virt_get_caches(caches); > table_offsets = g_array_new(false, true, > sizeof(uint32_t)); > > @@ -909,6 +912,10 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) > build_rimt(tables_blob, tables->linker, s); > } > > + acpi_add_table(table_offsets, tables_blob); > + build_pptt(tables_blob, tables->linker, ms, s->oem_id, > + s->oem_table_id, num_caches, caches); > + > acpi_add_table(table_offsets, tables_blob); > > if (ms->acpi_spcr_enabled) { > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index d4b501802f60..c84b17a40125 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -109,6 +109,45 @@ static const MemMapEntry virt_memmap[] = { > [VIRT_DRAM] = { 0x80000000, 0x0 }, > }; > > +static CPUCoreCaches virt_caches[] = { > + { > + .type = DATA_CACHE, > + .sets = 256, > + .size = 64 * KiB, > + .level = 1, > + .linesize = 64, > + .attributes = 0x0, > + .associativity = 4, > + }, > + { > + .type = INSTRUCTION_CACHE, > + .sets = 256, > + .size = 64 * KiB, > + .level = 1, > + .linesize = 64, > + .attributes = 0x0, > + .associativity = 4, > + }, > + { > + .type = UNIFIED_CACHE, > + .sets = 4096, > + .size = 2048 * KiB, > + .level = 2, > + .linesize = 64, > + .attributes = 0x0, > + .associativity = 8, > + }, > + { > + .type = UNIFIED_CACHE, > + .sets = 8192, > + .size = 4096 * KiB, > + .level = 3, > + .linesize = 64, > + .attributes = 0x0, > + .associativity = 8, > + }, > +}; > + > /* PCIe high mmio is fixed for RV32 */ > #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL > #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) > @@ -140,6 +179,12 @@ static void virt_flash_map(RISCVVirtState *s, > sysmem, VIRT_FLASH_SECTOR_SIZE); > } > > +unsigned int virt_get_caches(CPUCoreCaches *caches) > +{ > + memcpy(caches, virt_caches, sizeof(virt_caches)); > + return ARRAY_SIZE(virt_caches); > +} > + > static void create_fdt_socket_plic(RISCVVirtState *s, > int socket, > uint32_t *phandle, uint32_t *intc_phandles, > @@ -1144,6 +1189,12 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data) > mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; > mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; > mc->numa_mem_supported = true; > + mc->smp_props.clusters_supported = true; > + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true; > + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true; > + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true; > + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true; > + > /* platform instead of architectural choice */ > mc->cpu_cluster_has_numa_boundary = true; > mc->default_ram_id = "riscv_virt_board.ram"; > diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h > index e516898f9ad9..1e498a4f5f6e 100644 > --- a/include/hw/riscv/virt.h > +++ b/include/hw/riscv/virt.h > @@ -121,10 +121,14 @@ enum { > #define VIRT_PLIC_SIZE(__num_context) \ > (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) > > +#define CPU_MAX_CACHES 16 > + > bool virt_is_acpi_enabled(RISCVVirtState *s); > bool virt_is_iommu_sys_enabled(RISCVVirtState *s); > void virt_acpi_setup(RISCVVirtState *vms); > > +unsigned int virt_get_caches(CPUCoreCaches *caches); > + > /* > * The virt machine physical address space used by some of the devices > * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,