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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?PDjxr5GDggwxaIsAaszILs6dVC0seIMpd+H1rh6Pkg0DQ+c9Vu/kCpvITYVs?= =?us-ascii?Q?jIPvO83IMv0BxEONzgAppQ91D5880RM7ZZEJPdOJMAX//t8zV9CebDBZCdtY?= =?us-ascii?Q?x9pUJ9xm3PPBkauCyr4wcuYoGXr8lXbuSTEBlC33/CQdZSC58R5u1YtgVXF3?= =?us-ascii?Q?GI3Ws3v7htI6CuCGQUxYrANHdcEQ/po9qVnjs6at5rirAN5DvceC1KGPHlp2?= =?us-ascii?Q?bRnZyfdzR06MzW8c5fB+enmkUNxEQCYUSUOfIx01X8bglLajmi2tC67b422n?= =?us-ascii?Q?wH8CvTHv0itOeD/9sxRzavDZoeFajkWBHvpEsbcnkTPXcVfH90kT3ZSNxzmy?= =?us-ascii?Q?fm9a2XJrCKNcmNHnzXT/TYUOVBUbu2+ZW0EekArwNxle2Uk5ZB1TgT3XZfuA?= =?us-ascii?Q?rwVQYIluHh7EmUgFwSIArTiOr8zs+f87KcItoW6ViBKVWKxRI4u2ZrMGawN8?= =?us-ascii?Q?AVp49kqd372+vuUq/nHdVa2L8ALJlUKmtwXdkw1uCMwH+PzTQaoagIXk58PE?= =?us-ascii?Q?6VAiFYN4HhlJEHShh64+tvrZ5nOl60aFpPUCFmuVJUiKEFaXs0ZzcnMONWOW?= =?us-ascii?Q?4ZboZgemWn2LIVOS09EkuPSRVMe3qM/siRGaR8K3WzH6ASLdOVZA3zbBuZHC?= =?us-ascii?Q?4HvQM9WqFp4dGJ1UbQ5yfPwC5nyBy3f9h2olmnqUlAB1guGliZ5Ehj0mwnmX?= =?us-ascii?Q?yccaZtiI4MS6tCIMt45nCls2aH6Fsqc7pCnY4xkSadQfDkJ7J6qU62IVYAV+?= =?us-ascii?Q?B4suvZNRdg5VaFQnaLJwYq/QOJkOEGgWV28tgNo4AI4jchvPtttjSDztogWa?= =?us-ascii?Q?zy2Xi5AUZzVUfD4TA4zYzYVCSowzi6cIHDEJ8THSPyAeHNT8ctVE1/nuLPDX?= =?us-ascii?Q?LnPQ5QF7Cp4U9KXcaUYOCgxX4M1haSXMmpu2UiaU8OBTUqZt1cg/mRGbV8lX?= =?us-ascii?Q?0+rxc19cqylh7flhEfsFchD9GFY1FJ9p3WUstZBCsA2P96GIBnTLyLIbTWbx?= =?us-ascii?Q?rvd60PdZ9V/UzgnRjeLYwDVJzwFVAd4HqvPkqeuv8hp9YtrEgQ2VlFMBRDr3?= =?us-ascii?Q?FWzUngwNQoAHw9nTefNh1f9w60RY9thH9lPfE1F2nEkNihGT1+R7wvvrzKcf?= =?us-ascii?Q?CZXf7qNMThxDxeZgJky4RK6Ca5v2UKVgE032LYweBHrdv+tcTqrqI6DC23Wx?= =?us-ascii?Q?FFPJcTtI0a3+xKaqfYPQ3ZNDfCyhshf+QPfawUzoHsyLTXwPJzjiuGZBAFCl?= =?us-ascii?Q?Esn6zXV4E9EWdCmyTZehWl+uGE5CvFkOxvHLxE/gbN3CC7GnD0x/eNEU5vh7?= =?us-ascii?Q?EHA7ROQC/aqTTuqrKPwoFCzkrkRkQ8mML1DM0YJck7h9xliiSzc0IxJY8nar?= =?us-ascii?Q?5Xvo739ryR8Xbmi4Ca5yrySoz+wgdMA2SJ2xUp7Bo+lt/Cbgzpct/bWr4Krd?= =?us-ascii?Q?qSnDQ+DBG+vuQNlVk2+5prGWyQWWuSAAWlpUvsiIoLvtMy6xm3VexHU3Jr0v?= =?us-ascii?Q?rbPhldjTH5HtiD1O3yc+MpQbJsFzQlWB+10wPQXFWGSeXEwWyuANQjZrRCiI?= =?us-ascii?Q?w0UuaGQC2iCusGhyIdaT+Io1brt4Zsu4AQUgokclLw/s55vdXViP2GqHGz1X?= =?us-ascii?Q?qfBkOa2WXZLFldDXtyKH4Ek=3D?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: ceb90409-3896-4e75-6e22-08d99edcd44f X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5600.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2021 15:15:54.3014 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: rDv5bFrlfih6elkzdulXAoKiE3AJnGZV+ld8Oiqq53ZpuqY7agWfGmjY3pRN3HjBryElXw/Ly13adYrLgqb9CA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4605 On 03.11.2021 16:06, Roger Pau Monn=C3=A9 wrote: > On Wed, Nov 03, 2021 at 10:46:40AM +0100, Jan Beulich wrote: >> On 02.11.2021 12:03, Roger Pau Monn=C3=A9 wrote: >>> On Tue, Nov 02, 2021 at 11:13:08AM +0100, Jan Beulich wrote: >>>> On 25.10.2021 12:28, Roger Pau Monn=C3=A9 wrote: >>>>> On Thu, Oct 21, 2021 at 11:59:02AM +0200, Jan Beulich wrote: >>>>>> The two are really meant to be independent settings; iov_supports_xt= () >>>>>> using || instead of && was simply wrong. The corrected check is, >>>>>> however, redundant, just like the (correct) one in iov_detect(): The= se >>>>>> hook functions are unreachable without acpi_ivrs_init() installing t= he >>>>>> iommu_init_ops pointer, which it does only upon success. (Unlike for >>>>>> VT-d there is no late clearing of iommu_enable due to quirks, and an= y >>>>>> possible clearing of iommu_intremap happens only after iov_supports_= xt() >>>>>> has run.) >>>>>> >>>>>> Signed-off-by: Jan Beulich >>>>>> --- >>>>>> In fact in iov_detect() it could be iommu_enable alone which gets >>>>>> checked, but this felt overly aggressive to me. Instead I'm getting = the >>>>>> impression that the function may wrongly not get called when "iommu= =3Doff" >>>>>> but interrupt remapping is in use: We'd not get the interrupt handle= r >>>>>> installed, and hence interrupt remapping related events would never = get >>>>>> reported. (Same on VT-d, FTAOD.) >>>>> >>>>> I've spend a non-trivial amount of time looking into this before >>>>> reading this note. AFAICT you could set iommu=3Doff and still get x2A= PIC >>>>> enabled and relying on interrupt remapping. >>>> >>>> Right, contrary to ... >>>> >>>>>> For iov_supports_xt() the question is whether, like VT-d's >>>>>> intel_iommu_supports_eim(), it shouldn't rather check iommu_intremap >>>>>> alone (in which case it would need to remain a check rather than get= ting >>>>>> converted to ASSERT()). >>>>> >>>>> Hm, no, I don't think so. I think iommu_enable should take precedence >>>>> over iommu_intremap, and having iommu_enable =3D=3D false should forc= e >>>>> interrupt remapping to be reported as disabled. Note that disabling i= t >>>>> in iommu_setup is too late, as the APIC initialization will have >>>>> already taken place. >>>>> >>>>> It's my reading of the command line parameter documentation that >>>>> setting iommu=3Doff should disable all usage of the IOMMU, and that >>>>> includes the interrupt remapping support (ie: a user should not need >>>>> to set iommu=3Doff,no-intremap) >>>> >>>> ... that documentation. But I think it's the documentation that >>>> wants fixing, such that iommu=3Doff really only control DMA remap. >>> >>> IMO I think it's confusing to have sub-options that could be enabled >>> when you set the global one to off. I would expect `iommu=3Doff` to >>> disable all the iommu related options, and I think it's fair for >>> people to expect that behavior. >> >> It occurs to me that this reply of yours here contradicts your R-b >> on patch 1, in particular with its revision log saying: >> >> v2: Treat iommu_enable and iommu_intremap as separate options. >=20 > Right, I see. patch 1 uses >=20 > if ( !iommu_enable && !iommu_intremap ) > return; >=20 > Which I think should be: >=20 > if ( !iommu_enable ) > return; >=20 > Sorry I didn't realize in that context. I think we need to decide > whether we want to fix the documentation to match the code, or whether > we should fix the code to match the documentation. Except that adjusting the conditional(s) in patch 1 would then be a functional change that's not really the purpose of that patch - it really only folds acpi_ivrs_init()'s and acpi_parse_dmar()'s into a vendor-independent instance in acpi_iommu_init(). Alternatively we could adjust the conditional here (in patch 3), but that would feel unrelated once again, as this change is supposed to be AMD-specific. > My preference would be for the latter, because I think the resulting > interface would be clearer. That will require introducing a new > dmaremap iommu suboption, but again I think this will result in a > better interface overall. I guess we could do with a 3rd opinion: Paul, any chance? In any event I hope that we can agree that patches 1 and 2 are okay for 4.16 in their present shape, and patch 3 (plus whichever further ones) would better wait for post-4.16? Jan