Re: [PATCH v1] spi: pxa2xx: set clock divider according to rate

[Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>]

On 01/24/2018 01:59 PM, Andy Shevchenko wrote:
> On Skylake and recent Intel SoCs we have a fractional divider installed on the
> reference clock for SPI host controller. It allows to much more precisely set
> clock rate on the interface. Use it to get better rate approximation especially
> on lowest speed.
> 
> This has been tested on updated version of clk-fractional-divider.c that uses
> rational best approximation algorithm [1].
> 
> [1] http://www.spinics.net/lists/linux-clk/msg03135.html
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
> ---
>   drivers/spi/spi-pxa2xx.c | 30 +++++++++++++++++++++++-------
>   drivers/spi/spi-pxa2xx.h |  1 +
>   2 files changed, 24 insertions(+), 7 deletions(-)
...
> +static unsigned int spt_get_clk_div(struct driver_data *drv_data, int rate)
> +{
> +	const struct ssp_device *ssp = drv_data->ssp;
> +	struct chip_data *chip = drv_data->cur_chip;
> +	long round;
> +
> +	round = clk_round_rate(ssp->clk, rate);
> +	clk_set_rate(ssp->clk, round);
> +

Are you sure about this? If I remember correctly clk_set_rate() may 
sleep and here call chain originates from tasklet pump_transfers() -> 
pxa2xx_ssp_get_clk_div() -> spt_get_clk_div().

-- 
Jarkko
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