From: Stephen Boyd <sboyd@kernel.org>
To: Bjorn Andersson <andersson@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Luo Jie <quic_luoj@quicinc.com>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
quic_kkumarcs@quicinc.com, quic_suruchia@quicinc.com,
quic_pavir@quicinc.com, quic_linchen@quicinc.com,
quic_leiwei@quicinc.com, Luo Jie <quic_luoj@quicinc.com>
Subject: Re: [PATCH v2 2/4] clk: qcom: cmnpll: Add IPQ5424 SoC support
Date: Tue, 29 Apr 2025 12:58:14 -0700 [thread overview]
Message-ID: <ece226eb37c3a7c6d37798798332ea70@kernel.org> (raw)
In-Reply-To: <20250411-qcom_ipq5424_cmnpll-v2-2-7252c192e078@quicinc.com>
Quoting Luo Jie (2025-04-11 05:58:11)
> The CMN PLL in IPQ5424 SoC supplies the fixed clock to NSS at 300 MHZ
> and to PPE at 375 MHZ. Other output clocks from CMN PLL on this SoC,
> and their rates are same as IPQ9574.
>
> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
next prev parent reply other threads:[~2025-04-29 19:58 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-11 12:58 [PATCH v2 0/4] Add CMN PLL clock controller support for IPQ5424 Luo Jie
2025-04-11 12:58 ` [PATCH v2 1/4] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC Luo Jie
2025-04-11 20:59 ` Rob Herring (Arm)
2025-04-11 12:58 ` [PATCH v2 2/4] clk: qcom: cmnpll: Add IPQ5424 SoC support Luo Jie
2025-04-29 5:29 ` Jie Luo
2025-04-29 19:58 ` Stephen Boyd [this message]
2025-04-11 12:58 ` [PATCH v2 3/4] arm64: dts: ipq5424: Add CMN PLL node Luo Jie
2025-04-11 12:58 ` [PATCH v2 4/4] arm64: dts: qcom: Update IPQ5424 xo_board to use fixed factor clock Luo Jie
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