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Thu, 23 Apr 2026 11:06:23 +0000 Message-ID: Date: Thu, 23 Apr 2026 13:06:20 +0200 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 02/11] drm/amdgpu/vce1: Check that the GPU address is < 128 MiB To: =?UTF-8?Q?Timur_Krist=C3=B3f?= , amd-gfx@lists.freedesktop.org, alexander.deucher@amd.com, John Olender References: <20260423011614.309180-1-timur.kristof@gmail.com> <20260423011614.309180-3-timur.kristof@gmail.com> Content-Language: en-US From: =?UTF-8?Q?Christian_K=C3=B6nig?= In-Reply-To: <20260423011614.309180-3-timur.kristof@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: BL0PR02CA0016.namprd02.prod.outlook.com (2603:10b6:207:3c::29) To PH7PR12MB5685.namprd12.prod.outlook.com (2603:10b6:510:13c::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH7PR12MB5685:EE_|SA5PPF590085732:EE_ X-MS-Office365-Filtering-Correlation-Id: 5ca5d81b-8110-444a-869d-08dea1285b38 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Note that in case of VCE1 the BAR > address is zero and we can't change it also due to the > firmware validator. > > When programming the mmVCE_VCPU_CACHE_OFFSETn registers, > don't AND them with a mask. This is incorrect because > the register mask is actually 0x0fffffff and useless because > we already ensure the addresses are below the limit. > > Signed-off-by: Timur Kristóf Reviewed-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/vce_v1_0.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > index 5b7b46d242c6d..edabec442cb63 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > @@ -313,17 +313,17 @@ static int vce_v1_0_mc_resume(struct amdgpu_device *adev) > > offset = adev->vce.gpu_addr + AMDGPU_VCE_FIRMWARE_OFFSET; > size = VCE_V1_0_FW_SIZE; > - WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); > + WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset); > WREG32(mmVCE_VCPU_CACHE_SIZE0, size); > > offset += size; > size = VCE_V1_0_STACK_SIZE; > - WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); > + WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset); > WREG32(mmVCE_VCPU_CACHE_SIZE1, size); > > offset += size; > size = VCE_V1_0_DATA_SIZE; > - WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); > + WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset); > WREG32(mmVCE_VCPU_CACHE_SIZE2, size); > > WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); > @@ -527,11 +527,15 @@ static int vce_v1_0_early_init(struct amdgpu_ip_block *ip_block) > * To accomodate that, we put GART to the LOW address range > * and reserve some GART pages where we map the VCPU BO, > * so that it gets a 32-bit address. > + * > + * The BAR address is zero and we can't change it > + * due to the firmware validation mechanism. > + * It seems that it fails to initialize if the address is >= 128 MiB. > */ > static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct amdgpu_device *adev) > { > u64 bo_size = amdgpu_bo_size(adev->vce.vcpu_bo); > - u64 max_vcpu_bo_addr = 0xffffffff - bo_size; > + u64 max_vcpu_bo_addr = 0x07ffffff - bo_size; > u64 num_pages = ALIGN(bo_size, AMDGPU_GPU_PAGE_SIZE) / AMDGPU_GPU_PAGE_SIZE; > u64 pa = amdgpu_gmc_vram_pa(adev, adev->vce.vcpu_bo); > u64 flags = AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | AMDGPU_PTE_VALID;