From: shuang.he@intel.com
To: shuang.he@intel.com, ethan.gao@intel.com,
intel-gfx@lists.freedesktop.org, ville.syrjala@linux.intel.com
Subject: Re: [PATCH 2/2] drm/i915: Fix chv cdclk support
Date: 03 Mar 2015 12:55:29 -0800 [thread overview]
Message-ID: <edcf24$dol3eg@FMSMGA003.fm.intel.com> (raw)
In-Reply-To: <1425319637-25733-2-git-send-email-ville.syrjala@linux.intel.com>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5872
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -7 278/278 271/278
ILK 308/308 308/308
SNB -1 284/284 283/284
IVB 380/380 380/380
BYT 294/294 294/294
HSW 387/387 387/387
BDW -1 316/316 315/316
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*PNV igt_gem_fence_thrash_bo-write-verify-none PASS(5) FAIL(1)PASS(1)
*PNV igt_gem_fence_thrash_bo-write-verify-x PASS(5) FAIL(1)PASS(1)
*PNV igt_gem_fence_thrash_bo-write-verify-y PASS(5) FAIL(1)NO_RESULT(1)
PNV igt_gem_userptr_blits_coherency-sync CRASH(5)NRUN(1)PASS(7) CRASH(2)
PNV igt_gem_userptr_blits_coherency-unsync NO_RESULT(1)CRASH(4)PASS(6) CRASH(1)PASS(1)
*PNV igt_gen3_render_linear_blits FAIL(3)DMESG_WARN(1)PASS(7) FAIL(1)NO_RESULT(1)
*PNV igt_gen3_render_mixed_blits FAIL(5)PASS(9) FAIL(1)NO_RESULT(1)
*SNB igt_gem_fence_thrash_bo-write-verify-y PASS(5) DMESG_WARN(1)PASS(1)
*BDW igt_gem_gtt_hog PASS(16) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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next prev parent reply other threads:[~2015-03-03 21:01 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-02 18:07 [PATCH 1/2] drm/i915: Allow pixel clock up to 95% of cdclk on CHV ville.syrjala
2015-03-02 18:07 ` [PATCH 2/2] drm/i915: Fix chv cdclk support ville.syrjala
2015-03-03 20:55 ` shuang.he [this message]
2015-03-09 8:59 ` Purushothaman, Vijay A
2015-03-09 9:24 ` Mohan Marimuthu, Yogesh
2015-03-09 15:40 ` Daniel Vetter
2015-03-09 8:58 ` [PATCH 1/2] drm/i915: Allow pixel clock up to 95% of cdclk on CHV Purushothaman, Vijay A
2015-03-09 9:23 ` Mohan Marimuthu, Yogesh
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