Re: [PATCH net-next v2 2/4] dt-bindings: net: dsa: Add SoC-e SWIP switch

[Andrew Lunn <andrew@lunn.ch>]

> > Since this is an FPGA, i assume there are no internal PHYs. Mixed mode
> > is not something FPGAs do. There are sometime "interesting"
> > relationships between port number and address on the MDIO bus. But
> > without internal PHYs you don't need to worry about this.
> > 
> 
> Correct, the FPGA IP has no internal PHYs. Each port is associated with
> a dedicated external MDIO bus.

How is a port and the MDIO bus associated?

Linux, in general, does not care. You have a collection of MDIO
busses, and on those busses you have a collection of PHYs. The MACs
use a phandle, or some other means to point to the PHY it should use.

Given this is a 31 port switch, why would you dedicate 62 pins to
MDIO, two per port, when you can put 32 PHYs on one MDIO bus?

So i doubt there is a strong association between port and MDIO bus.

What i could image is the one real MDIO bus controller is in global
scope within the RTL design. And then the logic to provide a port with
its multiplexor on that shared bus is in the per port RTL design
scope. I've not done much FPGA design, but i assume if you don't
connect the per port MDIO lines to anything, while place and route is
performed, they get optimised out?

> > So in theory, a 0 port switch is possible!
> 
> In theory, yes, but I prefer to treat it as invalid until it can be
> tested.

Yes, i would treat 0, 1 and probably 2 as invalid. 2 ports would
technically work in the DSA setup, but is pretty much pointless. It
only gets interesting with 3 ports or more.

     Andrew