From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57793) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bregc-0006Ul-BD for qemu-devel@nongnu.org; Wed, 05 Oct 2016 01:24:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bregW-00036d-7A for qemu-devel@nongnu.org; Wed, 05 Oct 2016 01:24:09 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:40093) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bregV-00036L-Uh for qemu-devel@nongnu.org; Wed, 05 Oct 2016 01:24:04 -0400 Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u955Nohr119254 for ; Wed, 5 Oct 2016 01:24:03 -0400 Received: from e23smtp02.au.ibm.com (e23smtp02.au.ibm.com [202.81.31.144]) by mx0a-001b2d01.pphosted.com with ESMTP id 25vp6v1q70-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 05 Oct 2016 01:24:03 -0400 Received: from localhost by e23smtp02.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 5 Oct 2016 15:24:00 +1000 References: <1475041518-9757-1-git-send-email-raji@linux.vnet.ibm.com> <1475041518-9757-2-git-send-email-raji@linux.vnet.ibm.com> <83513c4f-64d2-7c74-c017-504193f749f1@twiddle.net> From: Rajalakshmi Srinivasaraghavan Date: Wed, 5 Oct 2016 10:53:54 +0530 MIME-Version: 1.0 In-Reply-To: <83513c4f-64d2-7c74-c017-504193f749f1@twiddle.net> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Message-Id: Subject: Re: [Qemu-devel] [PATCH 1/6] target-ppc: add vmul10[u, eu, cu, ecu]q instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Cc: Vasant Hegde , qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com On 09/28/2016 10:12 PM, Richard Henderson wrote: > On 09/27/2016 10:45 PM, Rajalakshmi Srinivasaraghavan wrote: >> + val = tcg_const_i64(10); \ > Rename this "ten" for clarity? > >> + z = tcg_const_i64(0); \ >> + \ >> + if (add_cin) { \ >> + tcg_gen_andi_i64(cin, cpu_avrl[rB(ctx->opcode)], 0xF); \ >> + tcg_gen_movcond_i64(TCG_COND_LTU, cin, cin, val, cin, z); \ > What is the purpose of this movcond? The docs specifically say that values > greater than 9 are undefined. > >> + } else { \ >> + tcg_gen_movi_i64(cin, 0); \ >> + } \ >> + \ >> + tcg_gen_mulu2_i64(t0, t1, cpu_avrl[rA(ctx->opcode)], val); \ >> + tcg_gen_add2_i64(cpu_avrl[rD(ctx->opcode)], t2, t0, z, cin, z); \ >> + tcg_gen_add2_i64(t2, t0, t1, z, t2, z); \ > This two additions are unused if !add_cin, and the second appears to be > mergable with the first -- don't use so many z's. I think this simplifies to > > if (add_cin) { > tcg_gen_mulu2_i64(t0, t1, cpu_avrl[rA(ctx->opcode)], ten); > tcg_gen_andi_i64(t2, cpu_avrl[rB(ctx->opcode)], 0xF); > tcg_gen_add2_i64(cpu_avrl[rD(ctx->opcode)], t2, t0, t1, t2, z); > } else { > tcg_gen_mulu2_i64(cpu_avrl[rD(ctx->opcode)], t2, > cpu_avrl[rA(ctx->opcode)], ten); > } > >> + tcg_gen_mulu2_i64(t0, t1, cpu_avrh[rA(ctx->opcode)], val); \ >> + tcg_gen_add2_i64(cpu_avrh[rD(ctx->opcode)], t2, t0, z, t2, z); \ >> + \ >> + if (ret_carry) { \ >> + tcg_gen_add2_i64(cpu_avrl[rD(ctx->opcode)], t0, t1, z, t2, z); \ >> + tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); \ > Likewise simplifies to > > if (ret_carry) { > tcg_gen_mulu2_i64(t0, t1, cpu_avrh[rA(ctx->opcode)], ten); > tcg_gen_add2_i64(t0, cpu_avrl[rD(ctx->opcode)], t0, t1, t2, z); > tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); > } else { > tcg_gen_mul_i64(t0, cpu_avrh[rA(ctx->opcode)], ten); > tcg_gen_add_i64(cpu_avrh[rD(ctx->opcode)], t0, t2); > } > Will check and send updated patch. > r~ > > -- Thanks Rajalakshmi S