From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 6/8] drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op Date: Fri, 26 Oct 2012 12:13:39 +0100 Message-ID: References: <1351192548-2992-1-git-send-email-jbarnes@virtuousgeek.org> <1351192548-2992-6-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id CF5A89E8B3 for ; Fri, 26 Oct 2012 04:14:13 -0700 (PDT) In-Reply-To: <1351192548-2992-6-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, 25 Oct 2012 12:15:46 -0700, Jesse Barnes wrote: > So store into the scratch space of the HWS to make sure the invalidate > occurs. > > v2: use GTT address space for store, clean up #defines (Chris) > > Signed-off-by: Jesse Barnes > --- > @@ -1460,10 +1467,17 @@ static int blt_ring_flush(struct intel_ring_buffer *ring, > return ret; > > cmd = MI_FLUSH_DW; > + /* > + * Bspec vol 1c.3 - blitter engine command streamer: > + * "If ENABLED, all TLBs will be invalidated once the flush > + * operation is complete. This bit is only valid when the > + * Post-Sync Operation field is a value of 1h or 3h." > + */ > if (invalidate & I915_GEM_DOMAIN_RENDER) > - cmd |= MI_INVALIDATE_TLB; > + cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | > + MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_OP_STOREDW; > intel_ring_emit(ring, cmd); > - intel_ring_emit(ring, 0); > + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX | MI_FLUSH_DW_USE_GTT); s/SCRATCH_INDEX/SCRATCH_ADDR/ -Chris -- Chris Wilson, Intel Open Source Technology Centre