From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 6/8] drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op Date: Fri, 02 Nov 2012 12:41:00 +0000 Message-ID: References: <1351192548-2992-1-git-send-email-jbarnes@virtuousgeek.org> <1351192548-2992-6-git-send-email-jbarnes@virtuousgeek.org> <20121026094242.0c74d329@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A0009E77C for ; Fri, 2 Nov 2012 05:41:46 -0700 (PDT) In-Reply-To: <20121026094242.0c74d329@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, 26 Oct 2012 09:42:42 -0700, Jesse Barnes wrote: > commit b99c792eddf804150b3341a85c256df50d7ab5c2 > Author: Jesse Barnes > Date: Wed Sep 19 13:02:39 2012 -0700 > > drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3 > > So store into the scratch space of the HWS to make sure the invalidate > occurs. > > v2: use GTT address space for store, clean up #defines (Chris) > v3: use correct #define in blt ring flush (Chris) > > Signed-off-by: Jesse Barnes Reviewed-by: Chris Wilson That looks to be the code I executed, but I can't confirm it fixes any problems. References: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1063252 which looks to be a likely victim of a missing TLB flush on the blitter ring. -Chris -- Chris Wilson, Intel Open Source Technology Centre