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([2a02:908:1252:fb60:bf0c:d52c:6ba0:cfc6]) by smtp.gmail.com with ESMTPSA id g4sm13987185wro.12.2021.11.15.05.42.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Nov 2021 05:42:23 -0800 (PST) Subject: Re: [PATCH 1/2] drm/amdgpu: IH process reset count when restart To: Philip Yang , amd-gfx@lists.freedesktop.org References: <20211113000509.21407-1-Philip.Yang@amd.com> From: =?UTF-8?Q?Christian_K=c3=b6nig?= Message-ID: Date: Mon, 15 Nov 2021 14:42:21 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211113000509.21407-1-Philip.Yang@amd.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Felix.Kuehling@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 13.11.21 um 01:05 schrieb Philip Yang: > Otherwise when IH process restart, count is zero, the loop will > not exit to wake_up_all after processing AMDGPU_IH_MAX_NUM_IVS > interrupts. > > Signed-off-by: Philip Yang Reviewed-by: Christian König Maybe even CC: stable? Regards, Christian. > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c > index f3d62e196901..0c7963dfacad 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c > @@ -223,7 +223,7 @@ int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev, > */ > int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) > { > - unsigned int count = AMDGPU_IH_MAX_NUM_IVS; > + unsigned int count; > u32 wptr; > > if (!ih->enabled || adev->shutdown) > @@ -232,6 +232,7 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) > wptr = amdgpu_ih_get_wptr(adev, ih); > > restart_ih: > + count = AMDGPU_IH_MAX_NUM_IVS; > DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); > > /* Order reading of wptr vs. reading of IH ring data */