From: "Luck, Tony" <tony.luck@intel.com>
To: "Koralahalli Channabasappa, Smita" <skoralah@amd.com>,
Borislav Petkov <bp@alien8.de>,
Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Cc: "x86@kernel.org" <x86@kernel.org>,
"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"H . Peter Anvin" <hpa@zytor.com>,
"Dave Hansen" <dave.hansen@linux.intel.com>,
Yazen Ghannam <yazen.ghannam@amd.com>
Subject: RE: [RFC PATCH 1/2] x86/mce: Handle AMD threshold interrupt storms
Date: Wed, 23 Feb 2022 23:03:21 +0000 [thread overview]
Message-ID: <ef3e4bd4f8254b42a6d73356b4eec7f8@intel.com> (raw)
In-Reply-To: <3979d97f-464c-e1f4-d648-526b3121dd63@amd.com>
> It looks to me most of the code can be shared except in few places
> where AMD and Intel use different registers to set error thresholds.
Hopefully easy to abstract.
> And the fact that AMD's threshold interrupts just handles corrected
> errors unlike CMCI.
That makes your life much simpler than mine :-)
> I'm thinking of coming up with a shared code between both by keeping
> the Intel's new storm handling code as base and incorporating AMD
> changes on them and send for review.
>
> Let me know if thats okay?
My new Intel code hasn't had Boris look through it yet to point
out all the bits where I have bugs, or just make things more complex
than they need to be.
So it would be helpful if Boris could do at least a quick scan to
say my code is a worthy base. I'd hate to see you waste time
building a merged version and then have Boris say "Nack".
-Tony
next prev parent reply other threads:[~2022-02-23 23:03 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-17 14:16 [RFC PATCH 0/2] Handle AMD threshold interrupt storms Smita Koralahalli
2022-02-17 14:16 ` [RFC PATCH 1/2] x86/mce: " Smita Koralahalli
2022-02-17 17:28 ` Luck, Tony
2022-02-17 17:35 ` [PATCH 1/2] x86/mce: Remove old CMCI storm mitigation code Luck, Tony
2022-02-24 15:14 ` Borislav Petkov
2022-02-17 17:36 ` [PATCH 2/2] x86/mce: Add per-bank CMCI storm mitigation Luck, Tony
2022-02-23 22:11 ` Koralahalli Channabasappa, Smita
2022-03-07 13:31 ` Borislav Petkov
2022-03-07 20:04 ` Luck, Tony
2022-02-18 11:07 ` [RFC PATCH 1/2] x86/mce: Handle AMD threshold interrupt storms Borislav Petkov
2022-02-23 22:22 ` Koralahalli Channabasappa, Smita
2022-02-23 23:03 ` Luck, Tony [this message]
2022-03-15 18:15 ` [PATCH v2 0/2] New CMCI storm mitigation for Intel CPUs Tony Luck
2022-03-15 18:15 ` [PATCH v2 1/2] x86/mce: Remove old CMCI storm mitigation code Tony Luck
2022-03-15 18:15 ` [PATCH v2 2/2] x86/mce: Add per-bank CMCI storm mitigation Tony Luck
2022-03-15 18:34 ` [PATCH v2 0/2] New CMCI storm mitigation for Intel CPUs Borislav Petkov
2022-03-15 21:46 ` Koralahalli Channabasappa, Smita
2022-02-17 14:16 ` [RFC PATCH 2/2] x86/mce: Simplify code in log_and_reset_block() Smita Koralahalli
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