From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 353D1C433FE for ; Sat, 5 Dec 2020 18:22:13 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id A0BC02332A for ; Sat, 5 Dec 2020 18:22:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A0BC02332A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id E27234B0DC; Sat, 5 Dec 2020 13:22:11 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2dKyQmokeNdD; Sat, 5 Dec 2020 13:22:10 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id D2B0B4B154; Sat, 5 Dec 2020 13:22:10 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 3F9594B14F for ; Sat, 5 Dec 2020 13:22:09 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zo8+Gh8ewpeY for ; Sat, 5 Dec 2020 13:22:08 -0500 (EST) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 4666E4B0DC for ; Sat, 5 Dec 2020 13:22:08 -0500 (EST) Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 052B323138; Sat, 5 Dec 2020 18:22:07 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1klcC4-00GNe7-SK; Sat, 05 Dec 2020 18:22:05 +0000 MIME-Version: 1.0 Date: Sat, 05 Dec 2020 18:22:04 +0000 From: Marc Zyngier To: Daniel Lezcano Subject: Re: [PATCH v3 2/2] clocksource: arm_arch_timer: Correct fault programming of CNTKCTL_EL1.EVNTI In-Reply-To: References: <20201204073126.6920-1-zhukeqian1@huawei.com> <20201204073126.6920-3-zhukeqian1@huawei.com> User-Agent: Roundcube Webmail/1.4.9 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: daniel.lezcano@linaro.org, zhukeqian1@huawei.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, tglx@linutronix.de, catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, sean.j.christopherson@intel.com, julien.thierry.kdev@gmail.com, broonie@kernel.org, akpm@linux-foundation.org, alexios.zavras@intel.com, wanghaibin.wang@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: Andrew Morton , kvm@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, Sean Christopherson , Alexios Zavras , Will Deacon , Mark Brown , Thomas Gleixner , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Daniel, On 2020-12-05 11:15, Daniel Lezcano wrote: > Hi Marc, > > are you fine with this patch ? I am, although there still isn't any justification for the pos/lsb rework in the commit message (and calling that variable lsb is somewhat confusing). If you are going to apply it, please consider adding the additional comment below. > > > On 04/12/2020 08:31, Keqian Zhu wrote: >> ARM virtual counter supports event stream, it can only trigger an >> event >> when the trigger bit (the value of CNTKCTL_EL1.EVNTI) of CNTVCT_EL0 >> changes, >> so the actual period of event stream is 2^(cntkctl_evnti + 1). For >> example, >> when the trigger bit is 0, then virtual counter trigger an event for >> every >> two cycles. "While we're at it, rework the way we compute the trigger bit position by making it more obvious that when bits [n:n-1] are both set (with n being the most significant bit), we pick bit (n + 1)." With that: Acked-by: Marc Zyngier Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3D0AC4361A for ; Sat, 5 Dec 2020 18:23:50 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 98B1822287 for ; Sat, 5 Dec 2020 18:23:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 98B1822287 Authentication-Results: mail.kernel.org; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1klcCE-0008D7-1i; Sat, 05 Dec 2020 18:22:14 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1klcCA-0008Cn-De for linux-arm-kernel@lists.infradead.org; Sat, 05 Dec 2020 18:22:11 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 052B323138; Sat, 5 Dec 2020 18:22:07 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1klcC4-00GNe7-SK; Sat, 05 Dec 2020 18:22:05 +0000 MIME-Version: 1.0 Date: Sat, 05 Dec 2020 18:22:04 +0000 From: Marc Zyngier To: Daniel Lezcano Subject: Re: [PATCH v3 2/2] clocksource: arm_arch_timer: Correct fault programming of CNTKCTL_EL1.EVNTI In-Reply-To: References: <20201204073126.6920-1-zhukeqian1@huawei.com> <20201204073126.6920-3-zhukeqian1@huawei.com> User-Agent: Roundcube Webmail/1.4.9 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: daniel.lezcano@linaro.org, zhukeqian1@huawei.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, tglx@linutronix.de, catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, sean.j.christopherson@intel.com, julien.thierry.kdev@gmail.com, broonie@kernel.org, akpm@linux-foundation.org, alexios.zavras@intel.com, wanghaibin.wang@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201205_132210_544202_9B7A58D6 X-CRM114-Status: GOOD ( 11.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Morton , kvm@vger.kernel.org, Suzuki K Poulose , Catalin Marinas , linux-kernel@vger.kernel.org, Sean Christopherson , Alexios Zavras , Will Deacon , Mark Brown , James Morse , Julien Thierry , wanghaibin.wang@huawei.com, Thomas Gleixner , Keqian Zhu , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Daniel, On 2020-12-05 11:15, Daniel Lezcano wrote: > Hi Marc, > > are you fine with this patch ? I am, although there still isn't any justification for the pos/lsb rework in the commit message (and calling that variable lsb is somewhat confusing). If you are going to apply it, please consider adding the additional comment below. > > > On 04/12/2020 08:31, Keqian Zhu wrote: >> ARM virtual counter supports event stream, it can only trigger an >> event >> when the trigger bit (the value of CNTKCTL_EL1.EVNTI) of CNTVCT_EL0 >> changes, >> so the actual period of event stream is 2^(cntkctl_evnti + 1). For >> example, >> when the trigger bit is 0, then virtual counter trigger an event for >> every >> two cycles. "While we're at it, rework the way we compute the trigger bit position by making it more obvious that when bits [n:n-1] are both set (with n being the most significant bit), we pick bit (n + 1)." With that: Acked-by: Marc Zyngier Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6DD4C19437 for ; Sat, 5 Dec 2020 18:24:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B020C22287 for ; Sat, 5 Dec 2020 18:24:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727949AbgLESWw (ORCPT ); Sat, 5 Dec 2020 13:22:52 -0500 Received: from mail.kernel.org ([198.145.29.99]:52874 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726186AbgLESWr (ORCPT ); Sat, 5 Dec 2020 13:22:47 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 052B323138; Sat, 5 Dec 2020 18:22:07 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1klcC4-00GNe7-SK; Sat, 05 Dec 2020 18:22:05 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Sat, 05 Dec 2020 18:22:04 +0000 From: Marc Zyngier To: Daniel Lezcano Cc: Keqian Zhu , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Thomas Gleixner , Catalin Marinas , Will Deacon , James Morse , Suzuki K Poulose , Sean Christopherson , Julien Thierry , Mark Brown , Andrew Morton , Alexios Zavras , wanghaibin.wang@huawei.com Subject: Re: [PATCH v3 2/2] clocksource: arm_arch_timer: Correct fault programming of CNTKCTL_EL1.EVNTI In-Reply-To: References: <20201204073126.6920-1-zhukeqian1@huawei.com> <20201204073126.6920-3-zhukeqian1@huawei.com> User-Agent: Roundcube Webmail/1.4.9 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: daniel.lezcano@linaro.org, zhukeqian1@huawei.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, tglx@linutronix.de, catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, sean.j.christopherson@intel.com, julien.thierry.kdev@gmail.com, broonie@kernel.org, akpm@linux-foundation.org, alexios.zavras@intel.com, wanghaibin.wang@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hi Daniel, On 2020-12-05 11:15, Daniel Lezcano wrote: > Hi Marc, > > are you fine with this patch ? I am, although there still isn't any justification for the pos/lsb rework in the commit message (and calling that variable lsb is somewhat confusing). If you are going to apply it, please consider adding the additional comment below. > > > On 04/12/2020 08:31, Keqian Zhu wrote: >> ARM virtual counter supports event stream, it can only trigger an >> event >> when the trigger bit (the value of CNTKCTL_EL1.EVNTI) of CNTVCT_EL0 >> changes, >> so the actual period of event stream is 2^(cntkctl_evnti + 1). For >> example, >> when the trigger bit is 0, then virtual counter trigger an event for >> every >> two cycles. "While we're at it, rework the way we compute the trigger bit position by making it more obvious that when bits [n:n-1] are both set (with n being the most significant bit), we pick bit (n + 1)." With that: Acked-by: Marc Zyngier Thanks, M. -- Jazz is not dead. It just smells funny...