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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4835d92267bsm170571175e9.0.2026.02.12.07.11.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Feb 2026 07:11:50 -0800 (PST) Message-ID: Date: Thu, 12 Feb 2026 16:11:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 08/24] hw/arm/tegra241-cmdqv: Implement CMDQV init and vIOMMU allocation To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, clg@redhat.com, alex@shazbot.org, nicolinc@nvidia.com, nathanc@nvidia.com, mochs@nvidia.com, jan@nvidia.com, jgg@nvidia.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, kjaju@nvidia.com References: <20260206144823.80655-1-skolothumtho@nvidia.com> <20260206144823.80655-9-skolothumtho@nvidia.com> From: Eric Auger In-Reply-To: <20260206144823.80655-9-skolothumtho@nvidia.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: 1ytEhnnjisqK6wuafBnfHFZ495x6AFllE7WOb8blF4A_1770909112 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Hi Shameer, On 2/6/26 3:48 PM, Shameer Kolothum wrote: > From: Nicolin Chen > > Add initial Tegra241 CMDQV support by wiring up initialization and > IOMMUFD backed vIOMMU allocation. The CMDQV MMIO region and IRQ are > registered, while register handling remains a stub and will be completed > in subsequent patches. Explain what the MMIO region is made of (see below). Also describe what the interrupt is used for. what kind of interrupt is it? Also a work about the state (data)? > > Signed-off-by: Nicolin Chen > Signed-off-by: Shameer Kolothum > --- > hw/arm/tegra241-cmdqv.c | 55 ++++++++++++++++++++++++++++++++++++++--- > hw/arm/tegra241-cmdqv.h | 19 ++++++++++++++ > 2 files changed, 70 insertions(+), 4 deletions(-) > > diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c > index 6f30ca035b..596b1c5595 100644 > --- a/hw/arm/tegra241-cmdqv.c > +++ b/hw/arm/tegra241-cmdqv.c > @@ -13,6 +13,16 @@ > #include "smmuv3-accel.h" > #include "tegra241-cmdqv.h" > > +static uint64_t tegra241_cmdqv_read(void *opaque, hwaddr offset, unsigned size) > +{ > + return 0; > +} > + > +static void tegra241_cmdqv_write(void *opaque, hwaddr offset, uint64_t value, > + unsigned size) > +{ > +} > + > static void tegra241_cmdqv_free_veventq(SMMUv3State *s) > { > } > @@ -25,24 +35,61 @@ static bool tegra241_cmdqv_alloc_veventq(SMMUv3State *s, Error **errp) > > static void tegra241_cmdqv_free_viommu(SMMUv3State *s) > { > + SMMUv3AccelState *accel = s->s_accel; > + IOMMUFDViommu *viommu = accel->viommu; > + > + if (!viommu) { > + return; > + } > + iommufd_backend_free_id(viommu->iommufd, viommu->viommu_id); > } > > static bool > tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, > uint32_t *out_viommu_id, Error **errp) > { > - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); > - return false; > + Tegra241CMDQV *cmdqv = s->s_accel->cmdqv; > + > + if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, > + IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV, > + idev->hwpt_id, &cmdqv->cmdqv_data, > + sizeof(cmdqv->cmdqv_data), out_viommu_id, > + errp)) { > + error_append_hint(errp, "Tegra241 CMDQV support unavailable"); > + return false; > + } > + return true; > } > > static void tegra241_cmdqv_reset(SMMUv3State *s) > { > } > > +static const MemoryRegionOps mmio_cmdqv_ops = { > + .read = tegra241_cmdqv_read, > + .write = tegra241_cmdqv_write, > + .endianness = DEVICE_LITTLE_ENDIAN, > +}; > + > static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp) > { > - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); > - return false; > + SysBusDevice *sbd = SYS_BUS_DEVICE(OBJECT(s)); > + SMMUv3AccelState *accel = s->s_accel; > + Tegra241CMDQV *cmdqv; > + > + if (!accel) { > + error_setg(errp, "Tegra241 CMDQV requires SMMUv3 acceleration"); > + return false; > + } > + > + cmdqv = g_new0(Tegra241CMDQV, 1); > + memory_region_init_io(&cmdqv->mmio_cmdqv, OBJECT(s), &mmio_cmdqv_ops, cmdqv, > + "tegra241-cmdqv", TEGRA241_CMDQV_IO_LEN); > + sysbus_init_mmio(sbd, &cmdqv->mmio_cmdqv); > + sysbus_init_irq(sbd, &cmdqv->irq); > + cmdqv->s_accel = accel; > + accel->cmdqv = cmdqv; > + return true; > } > > static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops_impl = { > diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h > index 81c9deb384..6ea0087f61 100644 > --- a/hw/arm/tegra241-cmdqv.h > +++ b/hw/arm/tegra241-cmdqv.h > @@ -10,8 +10,27 @@ > #ifndef HW_TEGRA241_CMDQV_H > #define HW_TEGRA241_CMDQV_H > > +#include "smmuv3-accel.h" > #include CONFIG_DEVICES > > +/* > + * Tegra241 CMDQV MMIO layout (64KB pages): > + * > + * 0x00000: Global CMDQV registers I would use the spec terminology, something like TEGRA241_CMDQV_CFG TEGRA241_CMDQV_VCMDQ0 TEGRA241_CMDQV_VCMDQ1 TEGRA241_CMDQV_VINTF0 TEGRA241_CMDQV_VINTF1 Eric > + * 0x10000: Global VCMDQ registers, page 0 > + * 0x20000: Global VCMDQ registers, page 1 > + * 0x30000: VINTF0 logical VCMDQ registers, page 0 > + * 0x40000: VINTF0 logical VCMDQ registers, page 1 > + */ > +#define TEGRA241_CMDQV_IO_LEN 0x50000 > + > +typedef struct Tegra241CMDQV { > + struct iommu_viommu_tegra241_cmdqv cmdqv_data; > + SMMUv3AccelState *s_accel; > + MemoryRegion mmio_cmdqv; > + qemu_irq irq; > +} Tegra241CMDQV; > + > #ifdef CONFIG_TEGRA241_CMDQV > const SMMUv3AccelCmdqvOps *tegra241_cmdqv_ops(void); > #else