From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B610E33DECD for ; Fri, 6 Mar 2026 03:25:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772767556; cv=none; b=MlxABYo+6DkzdW8HHwGKV9afQ3JsIiyCiXmh234B4Gpv1gNannsKxQ2FrEOs9h62YSA2bcJ+Lv1cs64GYiZ2ab2E9BHsidM7C8oXduKDhk+MoII0OZDrVs2KpRQsG0GKRBuCn5FBLySKnZQ6KKY/S04p6jGHLCGVdQz0qauTqUw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772767556; c=relaxed/simple; bh=Yc6hFHwiTmrxSF+/qL9x+vyoSiqgmClUy+bV4BuDjAM=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=i5bCREmSIFqvjJ44kMxety7hwA6P6a9fwun4I5+3b3flQgsGjs3QdPCBhebwvPjt8qtqSa3C/xgQx0Q3OsI+JWmXsyHr1tijQ5fhD2u7Qyoi7GmJrb0/1V7+rWgFhp1uyLkGc2GryG0F7qI9jib3TOBnOEkF1jf09sybJrrYYow= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YBOeJVhM; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YBOeJVhM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772767554; x=1804303554; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=Yc6hFHwiTmrxSF+/qL9x+vyoSiqgmClUy+bV4BuDjAM=; b=YBOeJVhMBZVyesltzui039gsSCynJE1hojmjE2vIk/pQUpJpav8gnFgM Hu9a7kYQTTC5Fx6ZicB8x1qKE2tS9tRxDeLWNrmVGt6rbG1qwsIfwBQg+ 8qRTzQQsfstzbMO+Rk33qCmXY17iX5o9xgfBLdFzn3X9IDcy+R9jt8Kol /GJYwdnWd6AYaf7xqy5vq0dmksLGmdtW/Sv2TGbiwYPgLXtx4IOO867Wk UH0W0eurAZV1sTiU8JHyRmSposvbTe8sL4sfiNuw0PyDJvdE1/GGCWRje ZDx8ernzwfOeTbcuqrnCB6h2izI33cZGxACTXUBUBGBEzx6eVGkYFcqud w==; X-CSE-ConnectionGUID: k0LmTxTnQNycsoWvSAbc9A== X-CSE-MsgGUID: h9FEQxxTRCaDL1EOcMyyIw== X-IronPort-AV: E=McAfee;i="6800,10657,11720"; a="74060581" X-IronPort-AV: E=Sophos;i="6.23,104,1770624000"; d="scan'208";a="74060581" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 19:25:54 -0800 X-CSE-ConnectionGUID: meFLeV7VTEq4D2v560TKhQ== X-CSE-MsgGUID: TBINicLMQL6nvWWjrW4UEQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,104,1770624000"; d="scan'208";a="216053631" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.241.147]) ([10.124.241.147]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 19:25:51 -0800 Message-ID: Date: Fri, 6 Mar 2026 11:25:49 +0800 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V3 08/13] target/i386: Make some PEBS features user-visible To: Zide Chen , qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas , Sandipan Das Cc: Xiaoyao Li , Dongli Zhang References: <20260304180713.360471-1-zide.chen@intel.com> <20260304180713.360471-9-zide.chen@intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20260304180713.360471-9-zide.chen@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit LGTM. Reviewed-by: Dapeng Mi On 3/5/2026 2:07 AM, Zide Chen wrote: > Populate selected PEBS feature names in FEAT_PERF_CAPABILITIES to make > the corresponding bits user-visible CPU feature knobs, allowing them to > be explicitly enabled or disabled via -cpu +/-. > > Once named, these bits become part of the guest CPU configuration > contract. If a VM is configured with such a feature enabled, migration > to a destination that does not support the feature may fail, as the > destination cannot honor the guest-visible CPU model. > > The PEBS_FMT bits are not exposed, as target/i386 currently does not > support multi-bit CPU properties. > > Co-developed-by: Dapeng Mi > Signed-off-by: Dapeng Mi > Signed-off-by: Zide Chen > --- > V2: > - Add the missing comma after "pebs-arch-reg". > - Simplify the PEBS_FMT description in the commit message. > --- > target/i386/cpu.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index a69c3108f64b..89691fba45e1 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -1618,10 +1618,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > .type = MSR_FEATURE_WORD, > .feat_names = { > NULL, NULL, NULL, NULL, > + NULL, NULL, "pebs-trap", "pebs-arch-reg", > NULL, NULL, NULL, NULL, > - NULL, NULL, NULL, NULL, > - NULL, "full-width-write", NULL, NULL, > - NULL, NULL, NULL, NULL, > + NULL, "full-width-write", "pebs-baseline", NULL, > + NULL, "pebs-timing-info", NULL, NULL, > NULL, NULL, NULL, NULL, > NULL, NULL, NULL, NULL, > NULL, NULL, NULL, NULL,