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Mon, 25 May 2026 09:36:51 -0700 (PDT) Received: from [192.55.54.43] ([192.55.54.43]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-304522314a4sm7981376eec.18.2026.05.25.09.36.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 May 2026 09:36:50 -0700 (PDT) Message-ID: Date: Mon, 25 May 2026 19:36:46 +0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH i-g-t 2/8] lib/intel_batchbuffer: make __intel_bb_create gt aware To: "Naladala, Ramanaidu" , igt-dev@lists.freedesktop.org References: <20260323162911.1912755-1-juhapekka.heikkila@gmail.com> <20260323162911.1912755-3-juhapekka.heikkila@gmail.com> <3ad90035-1f0e-4084-9042-ccbd00cbb644@intel.com> Content-Language: en-US From: =?UTF-8?Q?Juha-Pekka_Heikkil=C3=A4?= In-Reply-To: <3ad90035-1f0e-4084-9042-ccbd00cbb644@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" On 18/04/2026 07.26, Naladala, Ramanaidu wrote: > Hi JP, > > On 3/23/2026 9:59 PM, Juha-Pekka Heikkila wrote: >> add possibility to use gt id in __intel_bb_create >> >> Signed-off-by: Juha-Pekka Heikkila >> --- >> lib/intel_batchbuffer.c | 20 +++++++++++--------- >> lib/intel_batchbuffer.h | 1 + >> 2 files changed, 12 insertions(+), 9 deletions(-) >> >> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c >> index b09506574..802e771a4 100644 >> --- a/lib/intel_batchbuffer.c >> +++ b/lib/intel_batchbuffer.c >> @@ -905,7 +905,8 @@ static struct intel_bb * >> __intel_bb_create(int fd, uint32_t ctx, uint32_t vm, const intel_ctx_cfg_t *cfg, >> uint32_t size, bool do_relocs, >> uint64_t start, uint64_t end, uint64_t alignment, >> - uint8_t allocator_type, enum allocator_strategy strategy, uint64_t region) >> + uint8_t allocator_type, enum allocator_strategy strategy, >> + uint64_t region, uint16_t gt_id) > Update the function document with new argument. >> { >> struct drm_i915_gem_exec_object2 *object; >> struct intel_bb *ibb = calloc(1, sizeof(*ibb)); >> @@ -915,6 +916,7 @@ __intel_bb_create(int fd, uint32_t ctx, uint32_t vm, const intel_ctx_cfg_t *cfg, >> ibb->devid = intel_get_drm_devid(fd); >> ibb->gen = intel_gen(ibb->devid); >> ibb->ctx = ctx; >> + ibb->gt_id = gt_id; >> >> ibb->fd = fd; >> ibb->driver = is_i915_device(fd) ? INTEL_DRIVER_I915 : >> @@ -1059,7 +1061,7 @@ struct intel_bb *intel_bb_create_full(int fd, uint32_t ctx, uint32_t vm, >> enum allocator_strategy strategy, uint64_t region) >> { >> return __intel_bb_create(fd, ctx, vm, cfg, size, false, start, end, >> - alignment, allocator_type, strategy, region); >> + alignment, allocator_type, strategy, region, 0); >> } > The code always uses the magic number |0| for |gt_id|. Since |gt_id| is > passed explicitly to support multi-tile dGPU configurations, could we > read and assign |gt_id| dynamically instead of assuming |GT 0|? That would require verifying such functionality doesn't break any test running for gt, it's not in scope for this set. >> >> /** >> @@ -1086,7 +1088,7 @@ struct intel_bb *intel_bb_create_with_allocator(int fd, uint32_t ctx, uint32_t v >> { >> return __intel_bb_create(fd, ctx, vm, cfg, size, false, 0, 0, 0, >> allocator_type, ALLOC_STRATEGY_HIGH_TO_LOW, >> - is_i915_device(fd) ? REGION_SMEM : vram_if_possible(fd, 0)); >> + is_i915_device(fd) ? REGION_SMEM : vram_if_possible(fd, 0), 0); >> } >> >> static bool aux_needs_softpin(int fd) >> @@ -1128,7 +1130,7 @@ struct intel_bb *intel_bb_create(int fd, uint32_t size) >> relocs && !aux_needs_softpin(fd), 0, 0, 0, >> INTEL_ALLOCATOR_SIMPLE, >> ALLOC_STRATEGY_HIGH_TO_LOW, >> - is_i915 ? REGION_SMEM : vram_if_possible(fd, 0)); >> + is_i915 ? REGION_SMEM : vram_if_possible(fd, 0), 0); >> } >> >> /** >> @@ -1157,7 +1159,7 @@ intel_bb_create_with_context(int fd, uint32_t ctx, uint32_t vm, >> relocs && !aux_needs_softpin(fd), 0, 0, 0, >> INTEL_ALLOCATOR_SIMPLE, >> ALLOC_STRATEGY_HIGH_TO_LOW, >> - is_i915 ? REGION_SMEM : vram_if_possible(fd, 0)); >> + is_i915 ? REGION_SMEM : vram_if_possible(fd, 0), 0); >> } >> >> /** >> @@ -1184,7 +1186,7 @@ intel_bb_create_with_context_in_region(int fd, uint32_t ctx, uint32_t vm, >> return __intel_bb_create(fd, ctx, vm, cfg, size, >> relocs && !aux_needs_softpin(fd), 0, 0, 0, >> INTEL_ALLOCATOR_SIMPLE, >> - ALLOC_STRATEGY_HIGH_TO_LOW, region); >> + ALLOC_STRATEGY_HIGH_TO_LOW, region, 0); >> } >> >> /** >> @@ -1205,7 +1207,7 @@ struct intel_bb *intel_bb_create_with_relocs(int fd, uint32_t size) >> >> return __intel_bb_create(fd, 0, 0, NULL, size, true, 0, 0, 0, >> INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE, >> - REGION_SMEM); >> + REGION_SMEM, 0); >> } >> >> /** >> @@ -1231,7 +1233,7 @@ intel_bb_create_with_relocs_and_context(int fd, uint32_t ctx, >> >> return __intel_bb_create(fd, ctx, 0, cfg, size, true, 0, 0, 0, >> INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE, >> - REGION_SMEM); >> + REGION_SMEM, 0); >> } >> >> /** >> @@ -1256,7 +1258,7 @@ struct intel_bb *intel_bb_create_no_relocs(int fd, uint32_t size) >> return __intel_bb_create(fd, 0, 0, NULL, size, false, 0, 0, 0, >> INTEL_ALLOCATOR_SIMPLE, >> ALLOC_STRATEGY_HIGH_TO_LOW, >> - is_i915 ? REGION_SMEM : vram_if_possible(fd, 0)); >> + is_i915 ? REGION_SMEM : vram_if_possible(fd, 0), 0); >> } >> >> static void __intel_bb_destroy_relocations(struct intel_bb *ibb) >> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h >> index d0a7c8dc7..7049dd2d0 100644 >> --- a/lib/intel_batchbuffer.h >> +++ b/lib/intel_batchbuffer.h >> @@ -269,6 +269,7 @@ struct intel_bb { >> struct igt_pxp pxp; >> uint32_t ctx; >> uint32_t vm_id; >> + uint16_t gt_id; >> >> bool xe_bound; >> uint32_t engine_syncobj;