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From: Michal Simek <michal.simek@amd.com>
To: "Daniel Walker (danielwa)" <danielwa@cisco.com>,
	Michal Simek <michal.simek@xilinx.com>
Cc: "linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"Gopal Saha (gopasaha)" <gopasaha@cisco.com>,
	"xe-linux-external(mailer list)" <xe-linux-external@cisco.com>
Subject: Re: i2c-xiic driver changes from Cisco
Date: Thu, 4 Dec 2025 09:47:01 +0100	[thread overview]
Message-ID: <f2913b37-d259-406d-9f17-b1b5028cce6d@amd.com> (raw)
In-Reply-To: <aS8cG4Otywg1kIcr@goliath>

Hi,

On 12/2/25 18:04, Daniel Walker (danielwa) wrote:
> Hi,
> 
> We have a slightly modified version of the Xilinx IP which the i2c-xiic.c
> sources seem to support.
> 
> We made one (or at least one) change to the IP were we don't supply it with an
> interrupt line. It doesn't appear the driver supports this configuration.
> Is that accurate to your knowledge ?
> 
> If the drivers doesn't support some type of polling mode, is Xilinx willing to accept
> changes which would make the driver compatible with a polling mode if an
> interrupt is not supplied thru the device tree ?
> 
> It seems like it makes sense the driver should support a polling mode because
> Xilinx customers may make a product where the interrupt line doesn't function
> properly. In that case the customer would need a contingency which could be
> polling for interrupts.

Not sure what that change means but if you don't connect IRQ in design I expect 
vivado removes the whole logic around it at synthesis time.

Anyway using this IP without IRQ is perfectly valid use case and no issue from 
my side to also support it in the kernel.

Thanks,
Michal


      reply	other threads:[~2025-12-04  8:47 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-02 17:04 i2c-xiic driver changes from Cisco Daniel Walker (danielwa)
2025-12-04  8:47 ` Michal Simek [this message]

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