From: Stephen Boyd <sboyd@kernel.org>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Chen-Yu Tsai <wenst@chromium.org>,
Conor Dooley <conor+dt@kernel.org>,
Dan Carpenter <dan.carpenter@linaro.org>,
Daniel Golle <daniel@makrotopia.org>,
David S. Miller <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Frank Wunderlich <frank-w@public-files.de>,
Garmin.Chang <Garmin.Chang@mediatek.com>,
Jakub Kicinski <kuba@kernel.org>,
James Liao <jamesjj.liao@mediatek.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Michael Turquette <mturquette@baylibre.com>,
Paolo Abeni <pabeni@redhat.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Sabrina Dubroca <sd@queasysnail.net>,
Sam Shih <sam.shih@mediatek.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org, netdev@vger.kernel.org
Subject: Re: [PATCH v7 5/5] clk: mediatek: add drivers for MT7988 SoC
Date: Tue, 02 Jan 2024 16:53:13 -0800 [thread overview]
Message-ID: <f2ee0e96fc2467fdf44b960d0ffe94c1.sboyd@kernel.org> (raw)
In-Reply-To: <c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org>
Quoting Daniel Golle (2023-12-17 13:50:15)
> From: Sam Shih <sam.shih@mediatek.com>
>
> Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are
> typical MediaTek designs.
>
> Also add driver for XFIPLL clock generating the 156.25MHz clock for
> the XFI SerDes. It needs an undocumented software workaround and has
> an unknown internal design.
>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
Applied to clk-next
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Chen-Yu Tsai <wenst@chromium.org>,
Conor Dooley <conor+dt@kernel.org>,
Dan Carpenter <dan.carpenter@linaro.org>,
Daniel Golle <daniel@makrotopia.org>,
David S. Miller <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Frank Wunderlich <frank-w@public-files.de>,
Garmin.Chang <Garmin.Chang@mediatek.com>,
Jakub Kicinski <kuba@kernel.org>,
James Liao <jamesjj.liao@mediatek.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Michael Turquette <mturquette@baylibre.com>,
Paolo Abeni <pabeni@redhat.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Sabrina Dubroca <sd@queasysnail.net>,
Sam Shih <sam.shih@mediatek.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org, netdev@vger.kernel.org
Subject: Re: [PATCH v7 5/5] clk: mediatek: add drivers for MT7988 SoC
Date: Tue, 02 Jan 2024 16:53:13 -0800 [thread overview]
Message-ID: <f2ee0e96fc2467fdf44b960d0ffe94c1.sboyd@kernel.org> (raw)
In-Reply-To: <c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org>
Quoting Daniel Golle (2023-12-17 13:50:15)
> From: Sam Shih <sam.shih@mediatek.com>
>
> Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are
> typical MediaTek designs.
>
> Also add driver for XFIPLL clock generating the 156.25MHz clock for
> the XFI SerDes. It needs an undocumented software workaround and has
> an unknown internal design.
>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
Applied to clk-next
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next prev parent reply other threads:[~2024-01-03 0:53 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-17 21:49 [PATCH v7 1/5] dt-bindings: clock: mediatek: add MT7988 clock IDs Daniel Golle
2023-12-17 21:49 ` Daniel Golle
2023-12-17 21:49 ` [PATCH v7 2/5] dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs Daniel Golle
2023-12-17 21:49 ` Daniel Golle
2024-01-03 0:52 ` Stephen Boyd
2024-01-03 0:52 ` Stephen Boyd
2023-12-17 21:49 ` [PATCH v7 3/5] dt-bindings: clock: mediatek: add clock controllers of MT7988 Daniel Golle
2023-12-17 21:49 ` Daniel Golle
2023-12-18 7:48 ` Krzysztof Kozlowski
2023-12-18 7:48 ` Krzysztof Kozlowski
2024-01-03 0:52 ` Stephen Boyd
2024-01-03 0:52 ` Stephen Boyd
2023-12-17 21:50 ` [PATCH v7 4/5] clk: mediatek: add pcw_chg_bit control for PLLs " Daniel Golle
2023-12-17 21:50 ` Daniel Golle
2024-01-03 0:53 ` Stephen Boyd
2024-01-03 0:53 ` Stephen Boyd
2023-12-17 21:50 ` [PATCH v7 5/5] clk: mediatek: add drivers for MT7988 SoC Daniel Golle
2023-12-17 21:50 ` Daniel Golle
2024-01-03 0:53 ` Stephen Boyd [this message]
2024-01-03 0:53 ` Stephen Boyd
2024-01-03 0:52 ` [PATCH v7 1/5] dt-bindings: clock: mediatek: add MT7988 clock IDs Stephen Boyd
2024-01-03 0:52 ` Stephen Boyd
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