From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 93E44C433F5 for ; Fri, 24 Dec 2021 03:05:01 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4A74283515; Fri, 24 Dec 2021 04:04:59 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 369B9835EA; Fri, 24 Dec 2021 04:04:57 +0100 (CET) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.70.204]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id CD5D683510 for ; Fri, 24 Dec 2021 04:04:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=kever.yang@rock-chips.com Received: from localhost (unknown [192.168.167.13]) by regular1.263xmail.com (Postfix) with ESMTP id B50C8659; Fri, 24 Dec 2021 11:04:48 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-SKE-CHECKED: 1 X-ABS-CHECKED: 1 X-ANTISPAM-LEVEL: 2 Received: from [192.168.60.65] (unknown [103.29.142.67]) by smtp.263.net (postfix) whith ESMTP id P14040T140177634739968S1640315080276453_; Fri, 24 Dec 2021 11:04:47 +0800 (CST) X-IP-DOMAINF: 1 X-RL-SENDER: kever.yang@rock-chips.com X-SENDER: yk@rock-chips.com X-LOGIN-NAME: kever.yang@rock-chips.com X-FST-TO: u-boot@lists.denx.de X-RCPT-COUNT: 8 X-LOCAL-RCPT-COUNT: 3 X-MUTI-DOMAIN-COUNT: 0 X-SENDER-IP: 103.29.142.67 X-ATTACHMENT-NUM: 0 X-UNIQUE-TAG: <3403c2d0279c39f19fdeed54ad2edad8> X-System-Flag: 0 Subject: Re: [PATCH v3 3/3] rockchip: rk3568: add arch_cpu_init() To: sjg@chromium.org, philipp.tomsich@vrull.eu Cc: yamada.masahiro@socionext.com, chenjh@rock-chips.com, jason.zhu@rock-chips.com, trini@konsulko.com, yifeng.zhao@rock-chips.com, u-boot@lists.denx.de References: <20211026024221.5208-1-nico.cheng@rock-chips.com> <20211026103650.v3.3.Ib0d964f78ba35e91a4bef91d322101768d9fcfbf@changeid> From: Kever Yang Message-ID: Date: Fri, 24 Dec 2021 11:04:39 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20211026103650.v3.3.Ib0d964f78ba35e91a4bef91d322101768d9fcfbf@changeid> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On 2021/10/26 上午10:42, Nico Cheng wrote: > We configured the drive strength and security of EMMC in > arch_cpu_init(). > > Signed-off-by: Nico Cheng Reviewed-by: Kever Yang Thanks, - Kever > --- > > Changes in v3: > Replace configuration parameters of SGRF_SOC_CON4 with macro > definitions. > > Changes in v2: > We use the rk_clrreg function instead of the writel to set eMMC sdmmc0 to > secure. > Modify comments to make them more explicit. > > arch/arm/mach-rockchip/rk3568/rk3568.c | 27 +++++++++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c > index 973b4f9dcb..22eeb77d41 100644 > --- a/arch/arm/mach-rockchip/rk3568/rk3568.c > +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c > @@ -11,9 +11,18 @@ > #include > #include > > -#define PMUGRF_BASE 0xfdc20000 > -#define GRF_BASE 0xfdc60000 > - > +#define PMUGRF_BASE 0xfdc20000 > +#define GRF_BASE 0xfdc60000 > +#define GRF_GPIO1B_DS_2 0x218 > +#define GRF_GPIO1B_DS_3 0x21c > +#define GRF_GPIO1C_DS_0 0x220 > +#define GRF_GPIO1C_DS_1 0x224 > +#define GRF_GPIO1C_DS_2 0x228 > +#define GRF_GPIO1C_DS_3 0x22c > +#define SGRF_BASE 0xFDD18000 > +#define SGRF_SOC_CON4 0x10 > +#define EMMC_HPROT_SECURE_CTRL 0x03 > +#define SDMMC0_HPROT_SECURE_CTRL 0x01 > /* PMU_GRF_GPIO0D_IOMUX_L */ > enum { > GPIO0D1_SHIFT = 4, > @@ -81,5 +90,17 @@ void board_debug_uart_init(void) > > int arch_cpu_init(void) > { > +#ifdef CONFIG_SPL_BUILD > + /* Set the emmc sdmmc0 to secure */ > + rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11 > + | SDMMC0_HPROT_SECURE_CTRL << 4)); > + /* set the emmc driver strength to level 2 */ > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2); > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3); > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0); > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1); > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2); > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3); > +#endif > return 0; > }