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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id n24-20020a05651203f800b00501c8959f6asm2954228lfq.98.2023.10.26.03.36.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Oct 2023 03:36:53 -0700 (PDT) Message-ID: Date: Thu, 26 Oct 2023 12:36:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/5] arm64: dts: qcom: Add base SC8380XP dtsi and the QCP dts Content-Language: en-US To: Sibi Sankar , andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, catalin.marinas@arm.com, ulf.hansson@linaro.org Cc: agross@kernel.org, conor+dt@kernel.org, ayan.kumar.halder@amd.com, j@jannau.net, dmitry.baryshkov@linaro.org, nfraprado@collabora.com, m.szyprowski@samsung.com, u-kumar1@ti.com, peng.fan@nxp.com, lpieralisi@kernel.org, quic_rjendra@quicinc.com, abel.vesa@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, quic_tsoni@quicinc.com, neil.armstrong@linaro.org References: <20231025142427.2661-1-quic_sibis@quicinc.com> <20231025142427.2661-4-quic_sibis@quicinc.com> From: Konrad Dybcio In-Reply-To: <20231025142427.2661-4-quic_sibis@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 10/25/23 16:24, Sibi Sankar wrote: > From: Rajendra Nayak > > Add base dtsi and QCP board (Qualcomm Compute Platform) dts file for > SC8380XP SoC, describing the CPUs, GCC and RPMHCC clock controllers, > geni UART, interrupt controller, TLMM, reserved memory, interconnects, > SMMU and LLCC nodes. > > Co-developed-by: Abel Vesa > Signed-off-by: Abel Vesa > Signed-off-by: Rajendra Nayak > Co-developed-by: Sibi Sankar > Signed-off-by: Sibi Sankar > --- [...] > +&tlmm { > + gpio-reserved-ranges = <33 3>, <44 4>, <238 1>; It would be really cool if you added an explanation on why these GPIOs need to be reserved, especially since you can see what's connected on there on schematics. So, like: gpio-reserved-ranges = <33 3>, /* something */ <44 4>, /* something else (fp scanner?) <238 1>; /* UFS reset? */ [...] > + compatible = "qcom,oryon"; Again, this compatible won't fly unless all of these cores are totally identical and Oryon is only a name for this generation on this SoC (which I believe not to be the case). > + reg = <0x0 0x0>; > + enable-method = "psci"; > + next-level-cache = <&L1_0>; > + > + L1_0: l1-cache { > + compatible = "cache"; I'm not sure if L1 is supposed to be described in the DT, Krzysztof should know. > + next-level-cache = <&L2_0>; > + > + L2_0: l2-cache-0 { > + compatible = "cache"; cache-level? cache-unified? [...] > + memory@80000000 { > + device_type = "memory"; > + /* We expect the bootloader to fill in the size */ > + reg = <0 0x80000000 0 0x80000000>; That contradicts the comment you made above. Plus, 2 GiB seems a bit low for this SoC :D [...] > + gunyah_hyp_mem: gunyah-hyp-region@80000000 { you can probably strip the "-region" part, as this is implied by being a child of /reserved-memory > + pld_pep_mem: pld-pep-region@81f30000 { What's PLD? What's this region used for? PEP is a Windows invention. [...] > + av1_encoder_mem: av1-encoder-region@8e900000 { Is AV1enc hardware separate from iris? [...] > + gcc: clock-controller@100000 { > + compatible = "qcom,sc8380xp-gcc"; > + reg = <0 0x100000 0 0x200000>; The address part of reg should be padded to 8 hex digits. > + > + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, QCOM_ICC_TAG_ALWAYS would be nicer than 0 (see sa8775p) [...] > + > + interrupts = , One space after and before '=' Konrad From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 215F0C25B48 for ; Thu, 26 Oct 2023 10:37:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=VHKiBHo8B3trhZOc2tqtQ1CXeOUhsW/n71gQNJ/zaUc=; b=DBmsj518zm19WO 2dlgWMLh2TlhLFUVYUUl+MgI15ZBVqr68cji7VrVVQC6SBfbW/xt4CLbKxWh4EjLK36fJqT3MtPuQ HRK+X0Tz+etItqXOg1yGwOFVsjujDvcnfo6wfcAB10KUdNVeHKh/5f9AMsmI5jcegYKypORW7zpll t5ddZ3HKAceu545JGTbzZCVrnVSYgG5VdKNbafs4defGIaht9QpqEhNMaYNf8Zi/4Bg83vBx3zwnC nOy3RZEfCe4k5yKcKIjJz6yQVI1bB8Iq1MQPU40hP9wxP/ldCzQkx8KFZv/ZEsNXUjOhTjaiqe2bD 2tm0jADRDj3F2bEc3NBQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qvxjz-00EBbS-0C; Thu, 26 Oct 2023 10:37:27 +0000 Received: from mail-lf1-x12f.google.com ([2a00:1450:4864:20::12f]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qvxja-00EBWX-1f for linux-arm-kernel@lists.infradead.org; Thu, 26 Oct 2023 10:37:05 +0000 Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-507d7b73b74so946871e87.3 for ; Thu, 26 Oct 2023 03:36:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698316614; x=1698921414; darn=lists.infradead.org; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=mUjNYugWXfB4iPjrQerwJC5Hgqu+kEPnTtwC5PAjmHM=; b=B2r1OXPJGloI+ucy+b5s2VAkIYBty2R8Ydl3nkHF5QTxoJXeFW1ai+al1yX525Me2n s09GQjIB7Pzl3yYJQ6IiD0DPAjgamNZZsiYZf3ggO6AIv9yTYuyyFQgOIqpUfKQ/jX1N jIDH94cXC07Iyvg9OZ/O9n0edqTuR+LhdWPAdUtPXkiLh/vUZcpWZGi0KaMwA0htHT45 2x9S33y0f928SEm4OtgZzk2Q7U34o7PRFQxIfS4D5nynv4HQ1f0WpBSKAghbv+o6d1Ru IVGunHfw8cYEF814WbfRyaxo0G8DCPIS1kvg5S5Exn5LDxxUXcCRXOwRj2huwJglvquQ HlFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698316614; x=1698921414; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=mUjNYugWXfB4iPjrQerwJC5Hgqu+kEPnTtwC5PAjmHM=; b=AXxV/c8g35vJ2glg6e3/3YDNlEtvSsTeXxoaeyMHP3TSbWcf2mxbWEYdYly+2O7dhw 1js7QichFI5YdlMZ5pEeW245bNIcqsCCDTBLpSibpoJoRVLx5kZ0PN5ERA3iWLNsFFXV 3en9ovP3vU0kXWjp9PhsdGDW8gqgRwHRg7NpY0R2xPfURSwFHt1qY/7lIduGLf6zUoxj y2C11OA84+/1mtlaI+hysKt4PTWbfKyquGOFat6Q5/pqygF777cBS+2kvaW/fbRKBgoZ XGB6J3isr34yglEFk1vqxPcuGVNR1CyjzMWR4RS5Rg7Xh50kU6wYV5eoxKJoZclPneMl jc9A== X-Gm-Message-State: AOJu0YyO4TEnu23Lmb5ELXbIij9/wVLcMR4tA9jep9hSZFgFNDxjvSGS NmFyR5xB6U/NUAjM9KdWsC/Rxw== X-Google-Smtp-Source: AGHT+IFR0kYrbz9KcWn983kcAAoVAZwmsmcMvoxTT7Cvu2H6TdPX2KPUjQ3lbuBZaawGsE3WlDdQZw== X-Received: by 2002:a19:4f04:0:b0:507:a001:792e with SMTP id d4-20020a194f04000000b00507a001792emr12867972lfb.46.1698316613735; Thu, 26 Oct 2023 03:36:53 -0700 (PDT) Received: from [172.30.204.123] (UNUSED.212-182-62-129.lubman.net.pl. [212.182.62.129]) by smtp.gmail.com with ESMTPSA id n24-20020a05651203f800b00501c8959f6asm2954228lfq.98.2023.10.26.03.36.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Oct 2023 03:36:53 -0700 (PDT) Message-ID: Date: Thu, 26 Oct 2023 12:36:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/5] arm64: dts: qcom: Add base SC8380XP dtsi and the QCP dts Content-Language: en-US To: Sibi Sankar , andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, catalin.marinas@arm.com, ulf.hansson@linaro.org Cc: agross@kernel.org, conor+dt@kernel.org, ayan.kumar.halder@amd.com, j@jannau.net, dmitry.baryshkov@linaro.org, nfraprado@collabora.com, m.szyprowski@samsung.com, u-kumar1@ti.com, peng.fan@nxp.com, lpieralisi@kernel.org, quic_rjendra@quicinc.com, abel.vesa@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, quic_tsoni@quicinc.com, neil.armstrong@linaro.org References: <20231025142427.2661-1-quic_sibis@quicinc.com> <20231025142427.2661-4-quic_sibis@quicinc.com> From: Konrad Dybcio In-Reply-To: <20231025142427.2661-4-quic_sibis@quicinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_033702_562449_508C28FD X-CRM114-Status: GOOD ( 15.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/25/23 16:24, Sibi Sankar wrote: > From: Rajendra Nayak > > Add base dtsi and QCP board (Qualcomm Compute Platform) dts file for > SC8380XP SoC, describing the CPUs, GCC and RPMHCC clock controllers, > geni UART, interrupt controller, TLMM, reserved memory, interconnects, > SMMU and LLCC nodes. > > Co-developed-by: Abel Vesa > Signed-off-by: Abel Vesa > Signed-off-by: Rajendra Nayak > Co-developed-by: Sibi Sankar > Signed-off-by: Sibi Sankar > --- [...] > +&tlmm { > + gpio-reserved-ranges = <33 3>, <44 4>, <238 1>; It would be really cool if you added an explanation on why these GPIOs need to be reserved, especially since you can see what's connected on there on schematics. So, like: gpio-reserved-ranges = <33 3>, /* something */ <44 4>, /* something else (fp scanner?) <238 1>; /* UFS reset? */ [...] > + compatible = "qcom,oryon"; Again, this compatible won't fly unless all of these cores are totally identical and Oryon is only a name for this generation on this SoC (which I believe not to be the case). > + reg = <0x0 0x0>; > + enable-method = "psci"; > + next-level-cache = <&L1_0>; > + > + L1_0: l1-cache { > + compatible = "cache"; I'm not sure if L1 is supposed to be described in the DT, Krzysztof should know. > + next-level-cache = <&L2_0>; > + > + L2_0: l2-cache-0 { > + compatible = "cache"; cache-level? cache-unified? [...] > + memory@80000000 { > + device_type = "memory"; > + /* We expect the bootloader to fill in the size */ > + reg = <0 0x80000000 0 0x80000000>; That contradicts the comment you made above. Plus, 2 GiB seems a bit low for this SoC :D [...] > + gunyah_hyp_mem: gunyah-hyp-region@80000000 { you can probably strip the "-region" part, as this is implied by being a child of /reserved-memory > + pld_pep_mem: pld-pep-region@81f30000 { What's PLD? What's this region used for? PEP is a Windows invention. [...] > + av1_encoder_mem: av1-encoder-region@8e900000 { Is AV1enc hardware separate from iris? [...] > + gcc: clock-controller@100000 { > + compatible = "qcom,sc8380xp-gcc"; > + reg = <0 0x100000 0 0x200000>; The address part of reg should be padded to 8 hex digits. > + > + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, QCOM_ICC_TAG_ALWAYS would be nicer than 0 (see sa8775p) [...] > + > + interrupts = , One space after and before '=' Konrad _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel