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Content-Language: en-US To: Kenneth Sloat , "sean.anderson@seco.com" , "michal.simek@xilinx.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" References: From: Michal Simek In-Reply-To: X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT034:EE_|LV2PR12MB5727:EE_ X-MS-Office365-Filtering-Correlation-Id: fa6e2764-51b7-4154-f57f-08dadeb743cb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: e2x+jmdASgUp4vQ3xlNHq3sRCY9WoU6CcVCJ6P3sQqO2xqvsZLmKMdo0uA8XBVa58r/Lbnz3Cbs48msGfSrI80CWRUJ9tRqZjIvf5m/VQZDTxrc1eNNrpjF6WT5/0HUuCe5ur1M6Y6c79JdLKyYI32AIdjdf2XlRtc9qsXNGtww4SQppr8lmi7i+dKbKa2es9RyYaDbukXE1AfjBOyTYZWfCzd6yH5j/TGdvAgakSKtL/HGKcE0/dHjNin+M8LdIj+SNVGdG5jMl/2U4Y5F4NyPPv6yQHVTx25ovlCwN7btckrNwcw/V0UOHT2cO/tz7wpzRjJCIEnUWLSPJQwIxbxcCZ0Ki3FPn3uDNwLaG9iKJTwaS12ve3WNDVQTgGKHTWtbkT6+nGTRcgR/+1PaJP0bv9+jlwErXSfLxc9LEfcOoLduw1DqNrqAlP90OPc3xEHaSkd0Cqu9JAi3lHKiZ8BX7qH0kdrjZf605PgZPzo24BEi/wZ4yOzTtD7T6ARv9DFoBhl6jd6PQ8Z3+OK7A+rrLU0t3FGsNe4KADArzQNAodqgeuBmSIVJvQrUinoODMHEELyfCB6VCtxSNjlxzcB3F1YV1ERX3g5brF/gy26/hUYZXroNfnRhd7CNLObcxsEhTgAwxq8cbH3MjAz/F2GENR7jE6G5VpGw8mqzZ/WdYrXXZKpIw9/yGnRgPgudWz9v9YPO89csiFlHzlsQ1sjBjxJ2l16ig8RnQ6/Gjf8+2SvihQdaiXJYucPlWrHvuGnJkrEgji1zPj06ub6UusQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:CA;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(376002)(39860400002)(346002)(396003)(451199015)(40470700004)(36840700001)(46966006)(36860700001)(83380400001)(8936002)(31696002)(86362001)(8676002)(81166007)(356005)(5660300002)(44832011)(82740400003)(2906002)(70586007)(70206006)(82310400005)(41300700001)(40480700001)(53546011)(26005)(16526019)(186003)(47076005)(426003)(2616005)(336012)(110136005)(16576012)(316002)(478600001)(40460700003)(31686004)(36756003)(43740500002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2022 16:13:12.3386 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa6e2764-51b7-4154-f57f-08dadeb743cb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5727 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221215_081322_015399_84F5C498 X-CRM114-Status: GOOD ( 25.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/15/22 17:07, Kenneth Sloat wrote: > From: Ken Sloat > > This timer HW supports 8, 16 and 32-bit timer widths. This > driver currently uses a u32 to store the max possible value > of the timer. However, statements perform addition of 2 in > xilinx_pwm_apply() when calculating the period_cycles and > duty_cycles values. Since priv->max is a u32, this will > result in an overflow to 1 which will not only be incorrect > but fail on range comparison. This results in making it > impossible to set the PWM in this timer mode. > > There are two obvious solutions to the current problem: > 1. Cast each instance where overflow occurs to u64. > 2. Change priv->max from a u32 to a u64. > > Solution #1 requires more code modifications, and leaves > opportunity to introduce similar overflows if other math > statements are added in the future. These may also go > undetected if running in non 32-bit timer modes. > > Solution #2 is the much smaller and cleaner approach and > thus the chosen method in this patch. > > This was tested on a Zynq UltraScale+ with multiple > instances of the PWM IP. > > Signed-off-by: Ken Sloat > --- > Changes in v2: > -Update commit comments to explain specifically where this > problem occurs as well as compare solutions. > > --- > include/clocksource/timer-xilinx.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/clocksource/timer-xilinx.h b/include/clocksource/timer-xilinx.h > index c0f56fe6d22a..d116f18de899 100644 > --- a/include/clocksource/timer-xilinx.h > +++ b/include/clocksource/timer-xilinx.h > @@ -41,7 +41,7 @@ struct regmap; > struct xilinx_timer_priv { > struct regmap *map; > struct clk *clk; > - u32 max; > + u64 max; > }; > > /** > -- > 2.17.1 Reviewed-by: Michal Simek Thanks, Michal _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 412ADC25B04 for ; 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Content-Language: en-US To: Kenneth Sloat , "sean.anderson@seco.com" , "michal.simek@xilinx.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" References: From: Michal Simek In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT034:EE_|LV2PR12MB5727:EE_ X-MS-Office365-Filtering-Correlation-Id: fa6e2764-51b7-4154-f57f-08dadeb743cb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: e2x+jmdASgUp4vQ3xlNHq3sRCY9WoU6CcVCJ6P3sQqO2xqvsZLmKMdo0uA8XBVa58r/Lbnz3Cbs48msGfSrI80CWRUJ9tRqZjIvf5m/VQZDTxrc1eNNrpjF6WT5/0HUuCe5ur1M6Y6c79JdLKyYI32AIdjdf2XlRtc9qsXNGtww4SQppr8lmi7i+dKbKa2es9RyYaDbukXE1AfjBOyTYZWfCzd6yH5j/TGdvAgakSKtL/HGKcE0/dHjNin+M8LdIj+SNVGdG5jMl/2U4Y5F4NyPPv6yQHVTx25ovlCwN7btckrNwcw/V0UOHT2cO/tz7wpzRjJCIEnUWLSPJQwIxbxcCZ0Ki3FPn3uDNwLaG9iKJTwaS12ve3WNDVQTgGKHTWtbkT6+nGTRcgR/+1PaJP0bv9+jlwErXSfLxc9LEfcOoLduw1DqNrqAlP90OPc3xEHaSkd0Cqu9JAi3lHKiZ8BX7qH0kdrjZf605PgZPzo24BEi/wZ4yOzTtD7T6ARv9DFoBhl6jd6PQ8Z3+OK7A+rrLU0t3FGsNe4KADArzQNAodqgeuBmSIVJvQrUinoODMHEELyfCB6VCtxSNjlxzcB3F1YV1ERX3g5brF/gy26/hUYZXroNfnRhd7CNLObcxsEhTgAwxq8cbH3MjAz/F2GENR7jE6G5VpGw8mqzZ/WdYrXXZKpIw9/yGnRgPgudWz9v9YPO89csiFlHzlsQ1sjBjxJ2l16ig8RnQ6/Gjf8+2SvihQdaiXJYucPlWrHvuGnJkrEgji1zPj06ub6UusQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:CA;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(376002)(39860400002)(346002)(396003)(451199015)(40470700004)(36840700001)(46966006)(36860700001)(83380400001)(8936002)(31696002)(86362001)(8676002)(81166007)(356005)(5660300002)(44832011)(82740400003)(2906002)(70586007)(70206006)(82310400005)(41300700001)(40480700001)(53546011)(26005)(16526019)(186003)(47076005)(426003)(2616005)(336012)(110136005)(16576012)(316002)(478600001)(40460700003)(31686004)(36756003)(43740500002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2022 16:13:12.3386 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa6e2764-51b7-4154-f57f-08dadeb743cb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5727 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/15/22 17:07, Kenneth Sloat wrote: > From: Ken Sloat > > This timer HW supports 8, 16 and 32-bit timer widths. This > driver currently uses a u32 to store the max possible value > of the timer. However, statements perform addition of 2 in > xilinx_pwm_apply() when calculating the period_cycles and > duty_cycles values. Since priv->max is a u32, this will > result in an overflow to 1 which will not only be incorrect > but fail on range comparison. This results in making it > impossible to set the PWM in this timer mode. > > There are two obvious solutions to the current problem: > 1. Cast each instance where overflow occurs to u64. > 2. Change priv->max from a u32 to a u64. > > Solution #1 requires more code modifications, and leaves > opportunity to introduce similar overflows if other math > statements are added in the future. These may also go > undetected if running in non 32-bit timer modes. > > Solution #2 is the much smaller and cleaner approach and > thus the chosen method in this patch. > > This was tested on a Zynq UltraScale+ with multiple > instances of the PWM IP. > > Signed-off-by: Ken Sloat > --- > Changes in v2: > -Update commit comments to explain specifically where this > problem occurs as well as compare solutions. > > --- > include/clocksource/timer-xilinx.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/clocksource/timer-xilinx.h b/include/clocksource/timer-xilinx.h > index c0f56fe6d22a..d116f18de899 100644 > --- a/include/clocksource/timer-xilinx.h > +++ b/include/clocksource/timer-xilinx.h > @@ -41,7 +41,7 @@ struct regmap; > struct xilinx_timer_priv { > struct regmap *map; > struct clk *clk; > - u32 max; > + u64 max; > }; > > /** > -- > 2.17.1 Reviewed-by: Michal Simek Thanks, Michal