Re: [RFC PATCH 15/36] arm64: replace local_daif helpers

[Vladimir Murzin <vladimir.murzin@arm.com>]

On 7/22/26 09:41, Jinjie Ruan wrote:
> 
> On 7/15/2026 5:26 PM, Liao, Chang wrote:
>> 在 2026/7/9 20:13, Vladimir Murzin 写道:
>>> From: Ada Couprie Diaz <ada.coupriediaz@arm.com>
>>>
>>> Replace existing `local_daif_...` usage with the new `local_all_irqs...`
>>> helpers, adding the necessary save-state struct where required.
>>>
>>> Slightly rework `apei_claim_sea()`'s handling of interrupt masking to
>>> fit with the new APIs.  Currently, it saves the DAIF flags to restore
>>> later and the `local_irq` ones to check if interrupts are disabled.
>>> It then masks AIF to signal the SEA (forcing DAIF masking), and will
>>> unmask to IF (re-enabling PMR masking if pseudo-NMIs are in use) if it
>>> interrupted a task with interrupts unmaksed, restoring with the DAIF
>>> flags from the beginning afterwards.
>>>
>>> As we want to preserve a "mask/unmask" process, change the logic from
>>> "mask AIF/unmask A/unmask IF" to "mask IF/mask A/unmask A/unmask IF" :
>>> first mask with `local_irq_save()`, mask/unmask further around the
>>> SEA signaling, and restore at the end with `local_irq_restore()`.
>>> Now that both APIs properly work with DAIF and PMR, this works
>>> as expected and also removes the need for a "save flags without masking"
>>> function for the new helpers, as this was the only user.
>>>
>>> Remove the use of GIC_PRIO_PSR_I_SET in `kvm/hyp/nvhe/switch.c`,
>>> as we now check both PMR and DAIF everywhere and we don't need to signal
>>> interrupts being masked in DAIF in the PMR anymore.
>>>
>>> As we removed the `daifflags.h` include in preparation for its removal,
>>> move `local_interrupt_priority_init()` to `asm/interrupts/masking.h`.
>>>
>>> Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
>>> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
>>> ---
>>>  arch/arm64/include/asm/daifflags.h          | 14 --------------
>>>  arch/arm64/include/asm/interrupts/masking.h | 14 ++++++++++++++
>>>  arch/arm64/kernel/acpi.c                    | 15 +++++++--------
>>>  arch/arm64/kernel/hibernate.c               | 16 ++++++++--------
>>>  arch/arm64/kernel/irq.c                     |  2 +-
>>>  arch/arm64/kernel/machine_kexec.c           |  4 ++--
>>>  arch/arm64/kernel/setup.c                   |  4 ++--
>>>  arch/arm64/kernel/smp.c                     | 14 +++++++-------
>>>  arch/arm64/kernel/suspend.c                 | 14 +++++++-------
>>>  arch/arm64/kvm/hyp/nvhe/switch.c            |  2 +-
>>>  arch/arm64/kvm/hyp/vgic-v3-sr.c             |  7 ++++---
>>>  arch/arm64/kvm/hyp/vhe/switch.c             | 12 +++++++-----
>>>  arch/arm64/mm/mmu.c                         |  7 ++++---
>>>  13 files changed, 64 insertions(+), 61 deletions(-)
>>>
>>> diff --git a/arch/arm64/include/asm/daifflags.h b/arch/arm64/include/asm/daifflags.h
>>> index 6b14ec4d4dbe..8f097a2d9099 100644
>>> --- a/arch/arm64/include/asm/daifflags.h
>>> +++ b/arch/arm64/include/asm/daifflags.h
>>> @@ -120,18 +120,4 @@ static __always_inline void local_daif_restore(unsigned long flags)
>>>  		trace_hardirqs_off();
>>>  }
>>>  
>>> -/*
>>> - * During early boot, we unmask PSR.DA before the GIC has been set up.
>>> - * If we use IRQ priority masking, the PMR and PSR will be out of sync
>>> - * after the GIC is enabled : sync them up.
>>> - */
>>> -static inline void local_interrupt_priority_init(void)
>>> -{
>>> -	WARN_ON(read_sysreg(daif) & PSR_A_BIT);
>>> -	lockdep_assert_irqs_disabled();
>>> -
>>> -	gic_write_pmr(GIC_PRIO_IRQOFF);
>>> -	write_sysreg(DAIF_PROCCTX, daif);
>>> -}
>>> -
>>>  #endif
>>> diff --git a/arch/arm64/include/asm/interrupts/masking.h b/arch/arm64/include/asm/interrupts/masking.h
>>> index 66ee03f7ab68..19d32618b2b9 100644
>>> --- a/arch/arm64/include/asm/interrupts/masking.h
>>> +++ b/arch/arm64/include/asm/interrupts/masking.h
>>> @@ -98,4 +98,18 @@ static inline void local_all_irqs_final_mask(void)
>>>  	trace_hardirqs_off();
>>>  }
>>>  #endif /* CONFIG_DEBUG_IRQFLAGS */
>>> +
>>> +/*
>>> + * During early boot, we unmask PSR.DA before the GIC has been set up.
>>> + * If we use IRQ priority masking, the PMR and PSR will be out of sync
>>> + * after the GIC is enabled : sync them up.
>>> + */
>>> +static inline void local_interrupt_priority_init(void)
>>> +{
>>> +	WARN_ON(read_sysreg(daif) & PSR_A_BIT);
>>> +	lockdep_assert_irqs_disabled();
>>> +
>>> +	arm64_update_exc_context(NOIRQ_CONTEXT, true);
>>> +}
>>> +
>>>  #endif /* __ASM_INTERRUPTS_MASKING_H */
>>> diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
>>> index 5891f92c2035..8ec784f96693 100644
>>> --- a/arch/arm64/kernel/acpi.c
>>> +++ b/arch/arm64/kernel/acpi.c
>>> @@ -33,7 +33,7 @@
>>>  #include <acpi/processor.h>
>>>  #include <asm/cputype.h>
>>>  #include <asm/cpu_ops.h>
>>> -#include <asm/daifflags.h>
>>> +#include <asm/interrupts/masking.h>
>>>  #include <asm/smp_plat.h>
>>>  
>>>  int acpi_noirq = 1;		/* skip ACPI IRQ initialization */
>>> @@ -391,15 +391,14 @@ int apei_claim_sea(struct pt_regs *regs)
>>>  	int err = -ENOENT;
>>>  	bool return_to_irqs_enabled;
>>>  	unsigned long current_flags;
>>> +	arm64_exc_hwstates_t all_irqs_state;
>>>  
>>>  	if (!IS_ENABLED(CONFIG_ACPI_APEI_GHES))
>>>  		return err;
>>>  
>>> -	current_flags = local_daif_save_flags();
>>> -
>>> -	/* current_flags isn't useful here as daif doesn't tell us about pNMI */
>>> -	return_to_irqs_enabled = !irqs_disabled_flags(arch_local_save_flags());
>>> +	local_irq_save(current_flags);
>>>  
>>> +	return_to_irqs_enabled = !irqs_disabled_flags(current_flags);
>>>  	if (regs)
>>>  		return_to_irqs_enabled = !regs_irqs_disabled(regs);
>>>  
>>> @@ -407,10 +406,11 @@ int apei_claim_sea(struct pt_regs *regs)
>>>  	 * SEA can interrupt SError, mask it and describe this as an NMI so
>>>  	 * that APEI defers the handling.
>>>  	 */
>>> -	local_daif_restore(DAIF_ERRCTX);
>>> +	all_irqs_state = local_all_irqs_save_mask(ERROR_CONTEXT);
>>>  	nmi_enter();
>>>  	err = ghes_notify_sea();
>>>  	nmi_exit();
>>> +	local_all_irqs_restore(all_irqs_state);
>>>  
>>>  	/*
>>>  	 * APEI NMI-like notifications are deferred to irq_work. Unless
>>> @@ -418,7 +418,6 @@ int apei_claim_sea(struct pt_regs *regs)
>>>  	 */
>>>  	if (!err) {
>>>  		if (return_to_irqs_enabled) {
>>> -			local_daif_restore(DAIF_PROCCTX_NOIRQ);
>>>  			__irq_enter();
>>>  			irq_work_run();
>>>  			__irq_exit();
>>> @@ -428,7 +427,7 @@ int apei_claim_sea(struct pt_regs *regs)
>>>  		}
>>>  	}
>>>  
>>> -	local_daif_restore(current_flags);
>>> +	local_irq_restore(current_flags);
>>>  
>>>  	return err;
>>>  }
>>> diff --git a/arch/arm64/kernel/hibernate.c b/arch/arm64/kernel/hibernate.c
>>> index d0d9bd91e639..4dd40593f736 100644
>>> --- a/arch/arm64/kernel/hibernate.c
>>> +++ b/arch/arm64/kernel/hibernate.c
>>> @@ -20,7 +20,7 @@
>>>  #include <asm/barrier.h>
>>>  #include <asm/cacheflush.h>
>>>  #include <asm/cputype.h>
>>> -#include <asm/daifflags.h>
>>> +#include <asm/interrupts/masking.h>
>>>  #include <asm/irqflags.h>
>>>  #include <asm/kexec.h>
>>>  #include <asm/memory.h>
>>> @@ -332,16 +332,16 @@ static void swsusp_mte_restore_tags(void)
>>>  
>>>  int swsusp_arch_suspend(void)
>>>  {
>>> -	int ret = 0;
>>> -	unsigned long flags;
>>>  	struct sleep_stack_data state;
>>> +	arm64_exc_hwstates_t flags;
>>> +	int ret = 0;
>>>  
>>>  	if (cpus_are_stuck_in_kernel()) {
>>>  		pr_err("Can't hibernate: no mechanism to offline secondary CPUs.\n");
>>>  		return -EBUSY;
>>>  	}
>>>  
>>> -	flags = local_daif_save();
>>> +	flags = local_all_irqs_save_mask(CRITICAL_CONTEXT);
>>>  
>>>  	if (__cpu_suspend_enter(&state)) {
>>>  		/* make the crash dump kernel image visible/saveable */
>>> @@ -391,7 +391,7 @@ int swsusp_arch_suspend(void)
>>>  		spectre_v4_enable_mitigation(NULL);
>>>  	}
>>>  
>>> -	local_daif_restore(flags);
>>> +	local_all_irqs_restore(flags);
>>>  
>>>  	return ret;
>>>  }
>>> @@ -405,11 +405,11 @@ int swsusp_arch_suspend(void)
>>>  int __nocfi swsusp_arch_resume(void)
>>>  {
>>>  	int rc;
>>> -	unsigned long flags;
>>>  	void *zero_page;
>>>  	size_t exit_size;
>>>  	pgd_t *tmp_pg_dir;
>>>  	phys_addr_t el2_vectors;
>>> +	arm64_exc_hwstates_t flags;
>>>  	void __noreturn (*hibernate_exit)(phys_addr_t, phys_addr_t, void *,
>>>  					  void *, phys_addr_t, phys_addr_t);
>>>  	struct trans_pgd_info trans_info = {
>>> @@ -476,11 +476,11 @@ int __nocfi swsusp_arch_resume(void)
>>>  	 *   swsusp_arch_resume(), and expects to be re-entered in the
>>>  	 *   same state : with all DAIF exceptions masked.
>>>  	 */
>>> -	flags = local_daif_save();
>>> +	flags = local_all_irqs_save_mask(CRITICAL_CONTEXT);
>>>  	hibernate_exit(virt_to_phys(tmp_pg_dir), resume_hdr.ttbr1_el1,
>>>  		       resume_hdr.reenter_kernel, restore_pblist,
>>>  		       resume_hdr.__hyp_stub_vectors, virt_to_phys(zero_page));
>>> -	local_daif_restore(flags);
>>> +	local_all_irqs_restore(flags);
>>>  
>>>  	return 0;
>>>  }
>>> diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c
>>> index c73faa30268d..36da80169aae 100644
>>> --- a/arch/arm64/kernel/irq.c
>>> +++ b/arch/arm64/kernel/irq.c
>>> @@ -21,7 +21,7 @@
>>>  #include <linux/seq_file.h>
>>>  #include <linux/smp.h>
>>>  #include <linux/vmalloc.h>
>>> -#include <asm/daifflags.h>
>>> +#include <asm/interrupts/masking.h>
>>>  #include <asm/exception.h>
>>>  #include <asm/numa.h>
>>>  #include <asm/softirq_stack.h>
>>> diff --git a/arch/arm64/kernel/machine_kexec.c b/arch/arm64/kernel/machine_kexec.c
>>> index c5693a32e49b..0ff45f918488 100644
>>> --- a/arch/arm64/kernel/machine_kexec.c
>>> +++ b/arch/arm64/kernel/machine_kexec.c
>>> @@ -17,7 +17,7 @@
>>>  
>>>  #include <asm/cacheflush.h>
>>>  #include <asm/cpu_ops.h>
>>> -#include <asm/daifflags.h>
>>> +#include <asm/interrupts/masking.h>
>>>  #include <asm/memory.h>
>>>  #include <asm/mmu.h>
>>>  #include <asm/mmu_context.h>
>>> @@ -173,7 +173,7 @@ void machine_kexec(struct kimage *kimage)
>>>  
>>>  	pr_info("Bye!\n");
>>>  
>>> -	local_daif_mask();
>>> +	local_all_irqs_final_mask();
>>>  
>>>  	/*
>>>  	 * Both restart and kernel_reloc will shutdown the MMU, disable data
>>> diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
>>> index 23c05dc7a8f2..14f283f7ac3a 100644
>>> --- a/arch/arm64/kernel/setup.c
>>> +++ b/arch/arm64/kernel/setup.c
>>> @@ -37,7 +37,7 @@
>>>  #include <asm/fixmap.h>
>>>  #include <asm/cpu.h>
>>>  #include <asm/cputype.h>
>>> -#include <asm/daifflags.h>
>>> +#include <asm/interrupts/masking.h>
>>>  #include <asm/elf.h>
>>>  #include <asm/cpufeature.h>
>>>  #include <asm/cpu_ops.h>
>>> @@ -311,7 +311,7 @@ void __init __no_sanitize_address setup_arch(char **cmdline_p)
>>>  	 * IRQ and FIQ will be unmasked after the root irqchip has been
>>>  	 * detected and initialized.
>>>  	 */
>>> -	local_daif_restore(DAIF_PROCCTX_NOIRQ);
>>> +	local_all_irqs_cpu_init_mask(NOIRQ_CONTEXT);
>>>  
>>>  	/*
>>>  	 * TTBR0 is only used for the identity mapping at this stage. Make it
>>> diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
>>> index b91cf163aac7..257d50529d14 100644
>>> --- a/arch/arm64/kernel/smp.c
>>> +++ b/arch/arm64/kernel/smp.c
>>> @@ -42,7 +42,7 @@
>>>  #include <asm/cpu.h>
>>>  #include <asm/cputype.h>
>>>  #include <asm/cpu_ops.h>
>>> -#include <asm/daifflags.h>
>>> +#include <asm/interrupts/masking.h>
>>>  #include <asm/kvm_mmu.h>
>>>  #include <asm/mmu_context.h>
>>>  #include <asm/numa.h>
>>> @@ -263,7 +263,7 @@ asmlinkage notrace void secondary_start_kernel(void)
>>>  	 * as the root irqchip has already been detected and initialized we can
>>>  	 * unmask IRQ and FIQ at the same time.
>>>  	 */
>>> -	local_daif_restore(DAIF_PROCCTX);
>>> +	local_all_irqs_cpu_init_mask(PROCESS_CONTEXT);
>>>  
>>>  	/*
>>>  	 * OK, it's off to the idle thread for us
>>> @@ -370,7 +370,7 @@ void __noreturn cpu_die(void)
>>>  
>>>  	idle_task_exit();
>>>  
>>> -	local_daif_mask();
>>> +	local_all_irqs_final_mask();
>>>  
>>>  	/* Tell cpuhp_bp_sync_dead() that this CPU is now safe to dispose of */
>>>  	cpuhp_ap_report_dead();
>>> @@ -870,7 +870,7 @@ static void __noreturn local_cpu_stop(unsigned int cpu)
>>>  {
>>>  	set_cpu_online(cpu, false);
>>>  
>>> -	local_daif_mask();
>>> +	local_all_irqs_final_mask();
>>>  	sdei_mask_local_cpu();
>>>  	cpu_park_loop();
>>>  }
>>> @@ -889,14 +889,14 @@ static void __noreturn ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs
>>>  {
>>>  #ifdef CONFIG_KEXEC_CORE
>>>  	/*
>>> -	 * Use local_daif_mask() instead of local_irq_disable() to make sure
>>> -	 * that pseudo-NMIs are disabled. The "crash stop" code starts with
>>> +	 * Use local_all_irqs_final_mask() instead of local_irq_disable() to make
>>> +	 * sure that pseudo-NMIs are disabled. The "crash stop" code starts with
>>>  	 * an IRQ and falls back to NMI (which might be pseudo). If the IRQ
>>>  	 * finally goes through right as we're timing out then the NMI could
>>>  	 * interrupt us. It's better to prevent the NMI and let the IRQ
>>>  	 * finish since the pt_regs will be better.
>>>  	 */
>>> -	local_daif_mask();
>>> +	local_all_irqs_final_mask();
>>>  
>>>  	crash_save_cpu(regs, cpu);
>>>  
>>> diff --git a/arch/arm64/kernel/suspend.c b/arch/arm64/kernel/suspend.c
>>> index c41724a40b75..d8c62d7e8922 100644
>>> --- a/arch/arm64/kernel/suspend.c
>>> +++ b/arch/arm64/kernel/suspend.c
>>> @@ -9,7 +9,7 @@
>>>  #include <asm/cacheflush.h>
>>>  #include <asm/cpufeature.h>
>>>  #include <asm/cpuidle.h>
>>> -#include <asm/daifflags.h>
>>> +#include <asm/interrupts/masking.h>
>>>  #include <asm/debug-monitors.h>
>>>  #include <asm/exec.h>
>>>  #include <asm/fpsimd.h>
>>> @@ -69,7 +69,7 @@ void notrace __cpu_suspend_exit(void)
>>>  	/*
>>>  	 * Restore HW breakpoint registers to sane values
>>>  	 * before debug exceptions are possibly reenabled
>>> -	 * by cpu_suspend()s local_daif_restore() call.
>>> +	 * by cpu_suspend()s local_all_irqs_save_mask() call.
>>>  	 */
>>>  	if (hw_breakpoint_restore)
>>>  		hw_breakpoint_restore(cpu);
>>> @@ -97,7 +97,7 @@ void notrace __cpu_suspend_exit(void)
>>>  int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
>>>  {
>>>  	int ret = 0;
>>> -	unsigned long flags;
>>> +	arm64_exc_hwstates_t flags;
>>>  	struct sleep_stack_data state;
>>>  
>>>  	/*
>>> @@ -119,12 +119,12 @@ int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
>>>  	 *
>>>  	 * Strictly speaking the trace_hardirqs_off() here is superfluous,
>>>  	 * hardirqs should be firmly off by now. This really ought to use
>>> -	 * something like raw_local_daif_save().
>>> +	 * something like raw_local_all_irqs_save_mask().
>>>  	 *
>>>  	 * This also unmasks interrupts in PMR in order to reliably
>>>  	 * resume if we're using pseudo-NMIs.
>>>  	 */
>>> -	flags = local_daif_save();
>>> +	flags = local_all_irqs_save_mask(CRITICAL_CONTEXT);
>>>  
>>>  	/*
>>>  	 * Function graph tracer state gets inconsistent when the kernel
>>> @@ -158,11 +158,11 @@ int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
>>>  	unpause_graph_tracing();
>>>  
>>>  	/*
>>> -	 * Restore pstate flags. OS lock and mdscr have been already
>>> +	 * Restore interrupt masks. OS lock and mdscr have been already
>>>  	 * restored, so from this point onwards, debugging is fully
>>>  	 * reenabled if it was enabled when core started shutdown.
>>>  	 */
>>> -	local_daif_restore(flags);
>>> +	local_all_irqs_restore(flags);
>>>  
>>>  	return ret;
>>>  }
>>> diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c
>>> index 7318e3e6a5f3..50566b455c80 100644
>>> --- a/arch/arm64/kvm/hyp/nvhe/switch.c
>>> +++ b/arch/arm64/kvm/hyp/nvhe/switch.c
>>> @@ -270,7 +270,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
>>>  	 * Naturally, we want to avoid this.
>>>  	 */
>>>  	if (system_uses_irq_prio_masking()) {
>>> -		gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
>>> +		gic_write_pmr(GIC_PRIO_IRQON);
>>>  		pmr_sync();
>>>  	}
>>>  
>>> diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-sr.c
>>> index c4d2f1feea8b..402d51430599 100644
>>> --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c
>>> +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c
>>> @@ -10,6 +10,7 @@
>>>  #include <linux/irqchip/arm-gic-v3.h>
>>>  #include <linux/kvm_host.h>
>>>  
>>> +#include <asm/interrupts/masking.h>
>>>  #include <asm/kvm_emulate.h>
>>>  #include <asm/kvm_hyp.h>
>>>  #include <asm/kvm_mmu.h>
>>> @@ -446,7 +447,7 @@ void __vgic_v3_init_lrs(void)
>>>  u64 __vgic_v3_get_gic_config(void)
>>>  {
>>>  	u64 val, sre;
>>> -	unsigned long flags = 0;
>>> +	arm64_exc_hwstates_t flags;
>>>  
>>>  	/*
>>>  	 * In compat mode, we cannot access ICC_SRE_EL1 at any EL
>>> @@ -476,7 +477,7 @@ u64 __vgic_v3_get_gic_config(void)
>>>  	 * of the exception entry to EL2.
>>>  	 */
>>>  	if (has_vhe()) {
>>> -		flags = local_daif_save();
>>> +		flags = local_all_irqs_save_mask(CRITICAL_CONTEXT);
>>>  	} else {
>>>  		sysreg_clear_set_hcr(0, HCR_AMO | HCR_FMO | HCR_IMO);
>>>  		isb();
>>> @@ -491,7 +492,7 @@ u64 __vgic_v3_get_gic_config(void)
>>>  	isb();
>>>  
>>>  	if (has_vhe()) {
>>> -		local_daif_restore(flags);
>>> +		local_all_irqs_restore(flags);
>>>  	} else {
>>>  		sysreg_clear_set_hcr(HCR_AMO | HCR_FMO | HCR_IMO, 0);
>>>  		isb();
>>> diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c
>>> index bbe9cebd3d9d..e7475d796f0a 100644
>>> --- a/arch/arm64/kvm/hyp/vhe/switch.c
>>> +++ b/arch/arm64/kvm/hyp/vhe/switch.c
>>> @@ -17,6 +17,7 @@
>>>  
>>>  #include <asm/barrier.h>
>>>  #include <asm/cpufeature.h>
>>> +#include <asm/interrupts/masking.h>
>>>  #include <asm/kprobes.h>
>>>  #include <asm/kvm_asm.h>
>>>  #include <asm/kvm_emulate.h>
>>> @@ -630,8 +631,9 @@ NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe);
>>>  int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
>>>  {
>>>  	int ret;
>>> +	arm64_exc_hwstates_t irqs_state;
>>>  
>>> -	local_daif_mask();
>>> +	irqs_state = local_all_irqs_save_mask(CRITICAL_CONTEXT);
>>>  
>>>  	/*
>>>  	 * Having IRQs masked via PMR when entering the guest means the GIC
>>> @@ -639,18 +641,18 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
>>>  	 * only way to get out will be via guest exceptions.
>>>  	 * Naturally, we want to avoid this.
>>>  	 *
>>> -	 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a
>>> -	 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU.
>>> +	 * local_all_irqs_save_mask() already sets GIC_PRIO_IRQON, we just need a
>>> +	 * dsb to ensure the redistributor forwards EL2 IRQs to the CPU.
>>>  	 */
>>>  	pmr_sync();
>> Since the new helper local_all_irqs_save_mask() already takes care of modifying ICC_PMR
>> and internally invokes pmr_sync() right after(from arm64_update_exc_hwstate()), keeping
>> this explicit pmr_sync() here is a bit redundant.
> It is indeed repeated here.
> 

Agreed. I'll update it in the next iteration.

Thanks
Vladimir

>>>  
>>>  	ret = __kvm_vcpu_run_vhe(vcpu);
>>>  
>>>  	/*
>>> -	 * local_daif_restore() takes care to properly restore PSTATE.DAIF
>>> +	 * local_all_irqs_restore() takes care to properly restore PSTATE.DAIF
>>>  	 * and the GIC PMR if the host is using IRQ priorities.
>>>  	 */
>>> -	local_daif_restore(DAIF_PROCCTX_NOIRQ);
>>> +	local_all_irqs_restore(irqs_state);
>>>  
>>>  	return ret;
>>>  }
>>> diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
>>> index f2be501468ce..f2c74911f5d9 100644
>>> --- a/arch/arm64/mm/mmu.c
>>> +++ b/arch/arm64/mm/mmu.c
>>> @@ -32,6 +32,7 @@
>>>  
>>>  #include <asm/barrier.h>
>>>  #include <asm/cputype.h>
>>> +#include <asm/interrupts/masking.h>
>>>  #include <asm/fixmap.h>
>>>  #include <asm/kasan.h>
>>>  #include <asm/kernel-pgtable.h>
>>> @@ -2307,7 +2308,7 @@ void __cpu_replace_ttbr1(pgd_t *pgdp, bool cnp)
>>>  	typedef void (ttbr_replace_func)(phys_addr_t);
>>>  	extern ttbr_replace_func idmap_cpu_replace_ttbr1;
>>>  	ttbr_replace_func *replace_phys;
>>> -	unsigned long daif;
>>> +	arm64_exc_hwstates_t all_irqs;
>>>  
>>>  	/* phys_to_ttbr() zeros lower 2 bits of ttbr with 52-bit PA */
>>>  	phys_addr_t ttbr1 = phys_to_ttbr(virt_to_phys(pgdp));
>>> @@ -2323,9 +2324,9 @@ void __cpu_replace_ttbr1(pgd_t *pgdp, bool cnp)
>>>  	 * We really don't want to take *any* exceptions while TTBR1 is
>>>  	 * in the process of being replaced so mask everything.
>>>  	 */
>>> -	daif = local_daif_save();
>>> +	all_irqs = local_all_irqs_save_mask(CRITICAL_CONTEXT);
>>>  	replace_phys(ttbr1);
>>> -	local_daif_restore(daif);
>>> +	local_all_irqs_restore(all_irqs);
>>>  
>>>  	cpu_uninstall_idmap();
>>>  }
>>