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[88.21.202.78]) by smtp.gmail.com with ESMTPSA id b17sm8497194wrp.49.2020.02.14.10.29.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 14 Feb 2020 10:29:48 -0800 (PST) Subject: Re: [PATCH 01/19] target/arm: Fix field extract from MVFR[0-2] To: Richard Henderson , qemu-devel@nongnu.org References: <20200214181547.21408-1-richard.henderson@linaro.org> <20200214181547.21408-2-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Fri, 14 Feb 2020 19:29:47 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200214181547.21408-2-richard.henderson@linaro.org> Content-Language: en-US X-MC-Unique: zw75TvMHOuS44eANu_TiMg-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/14/20 7:15 PM, Richard Henderson wrote: > These registers are 32-bits wide. Cut and paste used FIELD_EX64 > instead of the more proper FIELD_EX32. In practice all this did > was use an unnecessary 64-bit operation, producing correct results. >=20 > Signed-off-by: Richard Henderson > --- > target/arm/cpu.h | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) >=20 > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index e943ffe8a9..28cb2be6fc 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -3415,18 +3415,18 @@ static inline bool isar_feature_aa32_fp16_arith(c= onst ARMISARegisters *id) > static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id) > { > /* Return true if D16-D31 are implemented */ > - return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >=3D 2; > + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >=3D 2; > } > =20 > static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) > { > - return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0; > + return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; > } > =20 > static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) > { > /* Return true if CPU supports double precision floating point */ > - return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0; > + return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; > } > =20 > /* > @@ -3436,32 +3436,32 @@ static inline bool isar_feature_aa32_fpdp(const A= RMISARegisters *id) > */ > static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters = *id) > { > - return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0; > + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; > } > =20 > static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters = *id) > { > - return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1; > + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; > } > =20 > static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) > { > - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 1; > + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 1; > } > =20 > static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) > { > - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 2; > + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 2; > } > =20 > static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) > { > - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 3; > + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 3; > } > =20 > static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *i= d) > { > - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 4; > + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 4; > } > =20 > static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) >=20 Reviewed-by: Philippe Mathieu-Daud=C3=A9