From: shuang.he@intel.com
To: shuang.he@intel.com, ethan.gao@intel.com,
intel-gfx@lists.freedesktop.org, ville.syrjala@linux.intel.com
Subject: Re: [PATCH 4/4] drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV
Date: 12 Feb 2015 08:00:10 -0800 [thread overview]
Message-ID: <f539c7$k5kbel@fmsmga002.fm.intel.com> (raw)
In-Reply-To: <1423666790-11642-5-git-send-email-ville.syrjala@linux.intel.com>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5761
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 282/282 282/282
ILK 313/313 313/313
SNB 309/323 309/323
IVB 380/380 380/380
BYT 296/296 296/296
HSW -2 425/425 423/425
BDW -1 318/318 317/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
HSW igt_kms_flip_plain-flip-fb-recreate TIMEOUT(1)PASS(1) TIMEOUT(1)
HSW igt_kms_flip_plain-flip-fb-recreate-interruptible TIMEOUT(2)PASS(1) TIMEOUT(1)
*BDW igt_gem_gtt_hog PASS(6) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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prev parent reply other threads:[~2015-02-12 16:00 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-11 14:59 [PATCH 0/4] drm/i915: CHV display PHY magic ville.syrjala
2015-02-11 14:59 ` [PATCH 1/4] drm/i915: Implement chv display PHY lane stagger setup ville.syrjala
2015-02-11 14:59 ` [PATCH 2/4] drm/i915: Add a hack to fix link training errors on pipe A+port B on CHV ville.syrjala
2015-02-12 18:52 ` Ville Syrjälä
2015-02-11 14:59 ` [PATCH 3/4] Revert "drm/i915: Hack to tie both common lanes together on chv" ville.syrjala
2015-02-11 14:59 ` [PATCH 4/4] drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV ville.syrjala
2015-02-12 16:00 ` shuang.he [this message]
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