Re: [PATCH v10 00/17] Enable CXL PCIe Port Protocol Error handling and logging

["Bowman, Terry" <terry.bowman@amd.com>]

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On 7/23/2025 4:55 PM, dan.j.williams@intel.com wrote:
> Terry Bowman wrote:
>> This patchset updates CXL Protocol Error handling for CXL Ports and CXL
>> Endpoints (EP). The reach of this patchset grew from CXL Ports to include
>> EPs as well.
> [..]
>> == Testing ==
>> Testing results below shows the Upstream Switch Port UCE and EP UCE errors
>> are handled as PCI errors. This is because aer_get_device_error_info() does
>> not populate the AER error severity and status in the case of FATAL UCE on
>> Upstream Ports and Endpoints. This is intended because the USP link to
>> access the device can be compromised. The check for is_cxl_error() and
>> is_internal_error() fail as a result and then processes the error as a PCI
>> error. Also, the AER event logging is missing the PCIe AER status.
> Are those issues "TODO" or permanent quirks of the implementation?
>
> Although looking at the error message they all seem to correctly say "CXL
> Bus Error", I guess I am not seting the end user visible problem of the
> details you are pointing out here. I.e. LGTM.
This is a potential TODO. It needs to be investigated as a possible improvement
to gather fatal error details that will otherwise not be collected for upstream
CXL PCIe Ports and Endpoints. BTW, the check that results in empty aer_err_info 
is in is in aer_get_device_error_info().

The AER log's bus type is determined by aer_err_bus(). This function is only
checking pci_dev::is_cxl. As a result, this function returns CXL bus for all these
CXL device's errors.

The missing aer_err_info data for these devices results in is_cxl_error() returning false.
The error is then processed as a PCIe error. The PCIe EP UCE handler does check
for RAS status and panics() if a UCE is found. 

> [..]
>> == Root Port ==
>> root@tbowman-cxl:~/aer-inject# ./root-ce-inject.sh
> Where can I find these inject scripts?
>
I attached a cxl-aer-einj.tgz. It includes the scripts. It also includes the 
patch to enable UIE/CIE in the aer-inject userspace tool. It includes a cover 
with the remote branch and base details.

It does __not__ set the CXL RAS error. I have been using a debug patch (non-upstreamed) 
to set the RAS status. It's not ideal but allows me to test. I can clean 
that patch up and provide here if needed.
>> pcieport 0000:0c:00.0: aer_inject: Injecting errors 00004000/00000000 into device 0000:0c:00.0
>> pcieport 0000:0c:00.0: AER: Correctable error message received from 0000:0c:00.0
>> aer_event: 0000:0c:00.0 CXL Bus Error: severity=Corrected, Corrected Internal Error, TLP Header=Not available
>> pcieport 0000:0c:00.0: CXL Bus Error: severity=Correctable, type=Transaction Layer, (Receiver ID)
>> pcieport 0000:0c:00.0:   device [8086:7075] error status/mask=00004000/0000a000
>> pcieport 0000:0c:00.0:    [14] CorrIntErr    
>> cxl_aer_correctable_error: memdev=0000:0c:00.0 host=pci0000:0c serial=0 status='CRC Threshold Hit'
> Hmm, why "memdev=" for a root port error? Will take a look at what
> cxl_aer_correctable_error() is doing.

There was a discussion about this here:
https://lore.kernel.org/linux-cxl/aGSI7oXthPW-AY6D@aschofie-mobl2.lan/

> [..] 
>> base-commit: 716ba3023561ccacfaa28f988d26717535b8fed1
> I cannot find this commit in mainline nor linux-next. Please do try to
> base series on mainline tags, or otherwise push a public baseline branch
> somewhere. Helps reviewers and build bots.
The base commit in the cover sheet should have been: a403fe6c0b17 - cxl/edac: Fix potential memory leak issues

I somehow added a change to my local cxl/next branch. I'll delete and re-checkout remote/cxl/next and copy to cxl/next.
-Terry

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