From: Dave Hansen <dave.hansen@intel.com>
To: Brendan Jackman <jackmanb@google.com>, Borislav Petkov <bp@alien8.de>
Cc: Rik van Riel <riel@surriel.com>,
x86@kernel.org, linux-kernel@vger.kernel.org,
peterz@infradead.org, dave.hansen@linux.intel.com,
zhengqi.arch@bytedance.com, nadav.amit@gmail.com,
thomas.lendacky@amd.com, kernel-team@meta.com,
linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com,
mhklinux@outlook.com, andrew.cooper3@citrix.com,
Manali.Shukla@amd.com, mingo@kernel.org
Subject: Re: [PATCH v14 11/13] x86/mm: do targeted broadcast flushing from tlbbatch code
Date: Tue, 4 Mar 2025 09:51:48 -0800 [thread overview]
Message-ID: <f5fab528-c8fd-47ea-ba25-6d59ff517b03@intel.com> (raw)
In-Reply-To: <Z8cdQwVnx8dmFDLA@google.com>
On 3/4/25 07:33, Brendan Jackman wrote:
> On Tue, Mar 04, 2025 at 03:11:34PM +0100, Borislav Petkov wrote:
>> On Tue, Mar 04, 2025 at 12:52:47PM +0000, Brendan Jackman wrote:
>>> https://lore.kernel.org/all/CA+i-1C31TrceZiizC_tng_cc-zcvKsfXLAZD_XDftXnp9B2Tdw@mail.gmail.com/
>>
>> Lemme try to understand what you're suggesting on that subthread:
>>
>>> static inline void arch_start_context_switch(struct task_struct *prev)
>>> {
>>> arch_paravirt_start_context_switch(prev);
>>> tlb_start_context_switch(prev);
>>> }
>>
>> This kinda makes sense to me...
>
> Yeah so basically my concern here is that we are doing something
> that's about context switching, but we're doing it in mm-switching
> code, entangling an assumption that "context_switch() must either call
> this function or that function". Whereas if we just call it explicitly
> from context_switch() it will be much clearer.
I was coming to a similar conclusion. All of the nastiness here would
come from an operation like:
INVLPGB
=> get scheduled on another CPU
TLBSYNC
But there's no nastiness with:
INVLPGB
=> switch to init_mm
TLBSYNC
at *all*. Because the TLBSYNC still works just fine. In fact, it *has*
to work just fine because you can get an TLB flush IPI in that window
already.
>>> Now I think about it... if we always tlbsync() before a context switch, is the
>>> cant_migrate() above actually required? I think with that, even if we migrated
>>> in the middle of e.g. broadcast_kernel_range_flush(), we'd be fine? (At
>>> least, from the specific perspective of the invplgb code, presumably having
>>> preemption on there would break things horribly in other ways).
>>
>> I think we still need it because you need to TLBSYNC on the same CPU you've
>> issued the INVLPGB and actually, you want all TLBs to have been synched
>> system-wide.
>>
>> Or am I misunderstanding it?
>
> Er, I might be exposing my own ignorance here. I was thinking that you
> always go through context_switch() before you get migrated, but I
> might not understand hwo migration happens.
Let's take a step back. Most of our IPI-based TLB flushes end up in this
code:
preempt_disable();
smp_call_function_many_cond(...);
preempt_enable();
We don't have any fanciness around to keep the initiating thread on the
same CPU or check for pending TLB flushes at context switch time or lazy
tlb entry. We don't send asynchronous IPIs from the tlbbatch code and
then check for completion at batch finish time.
There's a lot of complexity to stuffing these TLB flushes into a
microarchitectural buffer and making *sure* they are flushed out.
INVLPGB is not free. It's not clear at all to me that doing loads of
them in reclaim code is superior to doing loads of:
inc_mm_tlb_gen(mm);
cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
and then just zapping the whole TLB on the next context switch.
I think we should defer this for now. Let's look at it again when there
are some performance numbers to justify it.
next prev parent reply other threads:[~2025-03-04 17:52 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-26 3:00 [PATCH v14 00/13] AMD broadcast TLB invalidation Rik van Riel
2025-02-26 3:00 ` [PATCH v14 01/13] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-03-05 21:36 ` [tip: x86/mm] x86/mm: Consolidate " tip-bot2 for Rik van Riel
2025-03-19 11:04 ` [tip: x86/core] " tip-bot2 for Rik van Riel
2025-09-02 15:44 ` [BUG] x86/mm: regression after 4a02ed8e1cc3 Giovanni Cabiddu
2025-09-02 15:50 ` Dave Hansen
2025-09-02 16:08 ` Nadav Amit
2025-09-02 16:11 ` Dave Hansen
2025-09-03 14:00 ` Rik van Riel
2025-09-02 16:05 ` Jann Horn
2025-09-02 16:13 ` Jann Horn
2025-09-03 14:18 ` Nadav Amit
2025-09-03 14:42 ` Jann Horn
2025-09-02 16:31 ` Jann Horn
2025-09-02 16:57 ` Giovanni Cabiddu
2025-02-26 3:00 ` [PATCH v14 02/13] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-02-28 16:21 ` Borislav Petkov
2025-02-28 19:27 ` Borislav Petkov
2025-03-05 21:36 ` [tip: x86/mm] x86/mm: Add INVLPGB feature and Kconfig entry tip-bot2 for Rik van Riel
2025-03-19 11:04 ` [tip: x86/core] " tip-bot2 for Rik van Riel
2025-02-26 3:00 ` [PATCH v14 03/13] x86/mm: add INVLPGB support code Rik van Riel
2025-02-28 18:46 ` Borislav Petkov
2025-02-28 18:51 ` Dave Hansen
2025-02-28 19:47 ` Borislav Petkov
2025-03-03 18:41 ` Dave Hansen
2025-03-03 19:23 ` Dave Hansen
2025-03-04 11:00 ` Borislav Petkov
2025-03-04 15:10 ` Dave Hansen
2025-03-04 16:19 ` Borislav Petkov
2025-03-04 16:57 ` Dave Hansen
2025-03-04 21:12 ` Borislav Petkov
2025-03-05 21:36 ` [tip: x86/mm] x86/mm: Add " tip-bot2 for Rik van Riel
2025-03-19 11:04 ` [tip: x86/core] " tip-bot2 for Rik van Riel
2025-02-26 3:00 ` [PATCH v14 04/13] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-02-28 19:00 ` Dave Hansen
2025-02-28 21:43 ` Borislav Petkov
2025-03-05 21:36 ` [tip: x86/mm] x86/mm: Use " tip-bot2 for Rik van Riel
2025-03-19 11:04 ` [tip: x86/core] " tip-bot2 for Rik van Riel
2025-02-26 3:00 ` [PATCH v14 05/13] x86/mm: use INVLPGB in flush_tlb_all Rik van Riel
2025-02-28 19:18 ` Dave Hansen
2025-03-01 12:20 ` Borislav Petkov
2025-03-01 15:54 ` Rik van Riel
2025-02-28 22:20 ` Borislav Petkov
2025-02-26 3:00 ` [PATCH v14 06/13] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-02-28 18:57 ` Borislav Petkov
2025-03-05 21:36 ` [tip: x86/mm] x86/mm: Use broadcast TLB flushing in page reclaim tip-bot2 for Rik van Riel
2025-03-19 11:04 ` [tip: x86/core] " tip-bot2 for Rik van Riel
2025-02-26 3:00 ` [PATCH v14 07/13] x86/mm: add global ASID allocation helper functions Rik van Riel
2025-03-02 7:06 ` Borislav Petkov
2025-03-05 21:36 ` [tip: x86/mm] x86/mm: Add " tip-bot2 for Rik van Riel
2025-03-19 11:04 ` [tip: x86/core] " tip-bot2 for Rik van Riel
2025-02-26 3:00 ` [PATCH v14 08/13] x86/mm: global ASID context switch & TLB flush handling Rik van Riel
2025-03-02 7:58 ` Borislav Petkov
2025-03-05 21:36 ` [tip: x86/mm] x86/mm: Handle global ASID context switch and TLB flush tip-bot2 for Rik van Riel
2025-03-19 11:04 ` [tip: x86/core] " tip-bot2 for Rik van Riel
2025-02-26 3:00 ` [PATCH v14 09/13] x86/mm: global ASID process exit helpers Rik van Riel
2025-03-02 12:38 ` Borislav Petkov
2025-03-02 13:53 ` Rik van Riel
2025-03-03 10:16 ` Borislav Petkov
2025-03-05 21:36 ` [tip: x86/mm] x86/mm: Add " tip-bot2 for Rik van Riel
2025-03-19 11:04 ` [tip: x86/core] " tip-bot2 for Rik van Riel
2025-02-26 3:00 ` [PATCH v14 10/13] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-03-03 10:57 ` Borislav Petkov
2025-03-05 21:36 ` [tip: x86/mm] x86/mm: Enable " tip-bot2 for Rik van Riel
2025-03-19 11:04 ` [tip: x86/core] " tip-bot2 for Rik van Riel
2025-02-26 3:00 ` [PATCH v14 11/13] x86/mm: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-03-03 11:46 ` Borislav Petkov
2025-03-03 21:47 ` Dave Hansen
2025-03-04 11:52 ` Borislav Petkov
2025-03-04 15:24 ` Dave Hansen
2025-03-04 12:52 ` Brendan Jackman
2025-03-04 14:11 ` Borislav Petkov
2025-03-04 15:33 ` Brendan Jackman
2025-03-04 17:51 ` Dave Hansen [this message]
2025-02-26 3:00 ` [PATCH v14 12/13] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-03-05 21:36 ` [tip: x86/mm] x86/mm: Enable " tip-bot2 for Rik van Riel
2025-03-19 11:04 ` [tip: x86/core] " tip-bot2 for Rik van Riel
2025-02-26 3:00 ` [PATCH v14 13/13] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-03-03 22:40 ` Dave Hansen
2025-03-04 11:53 ` Borislav Petkov
2025-03-03 12:42 ` [PATCH v14 00/13] AMD broadcast TLB invalidation Borislav Petkov
2025-03-03 13:29 ` Borislav Petkov
2025-03-04 12:04 ` [PATCH] x86/mm: Always set the ASID valid bit for the INVLPGB instruction Borislav Petkov
2025-03-04 12:43 ` Borislav Petkov
2025-03-05 21:36 ` [tip: x86/mm] " tip-bot2 for Tom Lendacky
2025-03-19 11:04 ` [tip: x86/core] " tip-bot2 for Tom Lendacky
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