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Message-ID: Date: Fri, 26 Sep 2025 13:38:30 +0300 User-Agent: Mozilla Thunderbird Subject: Re: [XEN][PATCH] x86/hvm: vlapic: fix RO bits emulation in LVTx regs To: Jan Beulich Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Alejandro Vallejo , Jason Andryuk , "xen-devel@lists.xenproject.org" References: <20250925195558.519568-1-grygorii_strashko@epam.com> Content-Language: en-US From: Grygorii Strashko In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: FR2P281CA0179.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:9f::15) To AS2PR03MB8907.eurprd03.prod.outlook.com (2603:10a6:20b:5e4::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS2PR03MB8907:EE_|DB8PR03MB6313:EE_ X-MS-Office365-Filtering-Correlation-Id: eaa834b5-3b0c-4df6-eea9-08ddfce8d649 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016; X-Microsoft-Antispam-Message-Info: =?utf-8?B?MHEwR0VoaWsrU0RQZDBzdkw0SHQwRzF1MEhZMDBaTFNtSDhnc05DVDJuZzFn?= =?utf-8?B?RVVDL0l5bmRpb3VkYlJzd25vRFJCeWVDVVZCT3RESXhPQW50bVJnc0tSSjlB?= =?utf-8?B?S0JNZHRoaTNBY0RDZ0haTzVOcEdVQlBuY2xoVU1XSFV6MklOVk8rYlhKcEw3?= =?utf-8?B?TlR1R1NmVXdLZ0UwbGkxK3paSGtTR3ZnUkhVZjlaaWZVNzZXN092VVZNZExt?= =?utf-8?B?ZW5ab2EvY2c5b2tSdHlYNHBSMU54aGZXMVVSS3RZVkV6ZHpJWnNCbnJvQWRZ?= =?utf-8?B?QktHWXdla2FrWWhrNytwZ2YxSFNZU2k4TWt5MFdybkRsTEcwRzdJRmV4SDA5?= =?utf-8?B?OFQ1Mkl4aWhpSWxOOW81bWJLTS9vQnZ0dnJVem9yTkpQdFYxYlNLclkvZW1V?= =?utf-8?B?SFNualJJOEY4MTZsd3lqbFR2SkNEVGJzVHFIS1hzNFFEYU5HY1FYOFZVWmMy?= =?utf-8?B?SnJpVHJpZG04MUdSYW9keDBmRTBwd3labzQvRnlHR2MyalhFSWYyck9HcnFC?= =?utf-8?B?R0JEMStBWVlKMFV6aFFyYTVnT0lEYndqTzZXcVpHUm42U1FFd0d5NGl2Nmth?= =?utf-8?B?amgwYUZHTHVIUXhYNlpkT2lETWZaV25JOWpiY2UrM1VQak1VZi90UFhlajAy?= =?utf-8?B?VWhOcXNwUmV6dW9CZ1A3NTJZek9NRzVVZi9XampVY2dvaEZwNHNXeFllaGxi?= =?utf-8?B?NFpDRVFjMExyMjVtQ0c5dUtqSm1RVXRxeFMyWXlkTU9EWU4yZDlLdlpGemlJ?= =?utf-8?B?djRDejc0SXppMUM5TzlVTTh5WUx4WElZN0ZwYXhxQ280eG5UbU9XTHVRWVNB?= =?utf-8?B?VEtVR0VjY0wycW1ESENCMFZ4TmZRNjMzdkJmTnNaaFFEY3hhQkd6NnlwQVN6?= =?utf-8?B?NW5aS1YwVVV3bGNoUzJ2bXlrZSt6UDh1di9PMGtPU3dka05vcEJmaVNFYXla?= =?utf-8?B?MFJRbENGOWM2K1N4bXZpbloyNTY0WW5DeEVpL1pBdXo0K1JlZ1lwSlgwMUMy?= =?utf-8?B?cXZlOG5MZHYzYzVVc203K2lIZmc4WlJwMU9sZXZJRGdyR1ZKL2d0R20wU3hw?= =?utf-8?B?aGd5eWVoaVA3dkdXemZDajhGNUNCQThCUHJvbHc2R3NYREllT21HN2svOGVE?= =?utf-8?B?ZEh4TUlKZDRGOFpSZDVjVzMyOTRpZWhUVWZ6WmlyWUl5SWcxcXBWUDluV0pP?= =?utf-8?B?MDVhaVo4VEpxN0EwTTRFYzN3aHc0d1hZbUt6WC9tWnNteThSMVJUNExmaldX?= =?utf-8?B?aTcvZ0U0RGE4U2QzR1RDOUZ6M2NaK3pQUDVtcTk5YXhJWk5lcFd4dG15VE9m?= =?utf-8?B?MEViWjZZakRlem5zMzVtMEhuWnFuaTBjYTAwQUpITUF2OG14NENqZWgrNEVi?= =?utf-8?B?ZDdWWm5NZUt1L2JvdHp0bEtoZmlyd20vaHB0b2tCMjlFejNmc0FNQjcyaUVF?= =?utf-8?B?NmsxVHBaRlBiK1RqWS9mRlNDa0ZGNzVKZGZxa2dXY1ZGN1lrRWdVTjlSekY2?= =?utf-8?B?U0ZnM1JMMlFWblp4anM1NG9wZUcwU0NMdHNET1V2cGJSUjY0czlLOXVoVVZQ?= =?utf-8?B?SDVzdktMaEQ2NC9YdWVoYmo5K1RRU2FuRTZPYnpRZlBYdGJDK0JqbnQxVkRj?= =?utf-8?B?anl4K1VubExTQTNaTzdYRE5RSTBvN0xPUTJxM0FEZXRXTGx4YW1EZlhtR2hS?= =?utf-8?B?bHNaemhNM2hPT05XVW04bDVoRi9TWjdqWEFhZlQrZWdmK2luTkxtSVJHbmkv?= =?utf-8?B?Vng2anFDMjE5SnJrZ3EvNnAzZ0hEcVd0WGpMOTNIZlVGYytrdk8zK1Zsem10?= =?utf-8?B?NG1JN2Z6dTVaRkt6UlJUdW8zUEszR2tNVjVHNTd1NDVYQit5bDNPcksrakFn?= =?utf-8?B?VzBzcXpZVTVKOGNSdU40YnJXUk03Y211SEcveTZYZzNrSW54MG9iQ2U4aE5x?= =?utf-8?Q?e6Xl9W7H+S0=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AS2PR03MB8907.eurprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(366016);DIR:OUT;SFP:1101; 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Me too. Usually RO/WI on most HW. For example, LAPIC MMIO "Write" will be ignored (WRMSR will trigger exception). > >> and the current vLAPIC implementations allows guest to write to these RO bits. >> >> The Delivery Status (DS) is not emulated by Xen - there is no IRQ msg bus, and >> the IRQ is: >> - or accepted at destination and appears as pending >> (vLAPIC Interrupt Request Register (IRR)) >> - or get rejected immediately. >> >> The Remote IRR Flag (RIR) behavior emulation is not implemented for LINT0/LINT1 >> in Xen for now. >> >> Hence it is definitely wrong to allow guest to write to LVTx regs RO bits, >> fix it by unconditionally cleaning up those bits in vlapic_reg_write(). >> >> Signed-off-by: Grygorii Strashko > > Please also add a Fixes: tag when correcting code. This is veeery old code. Probably f7c8af3a6476e ("[XEN] HVM: Clean up and simplify vlapic device-model code") or 50b3cef2eecb0 ("[HVM] Place all APIC registers into one page in native format.") > >> --- a/xen/arch/x86/hvm/vlapic.c >> +++ b/xen/arch/x86/hvm/vlapic.c >> @@ -880,6 +880,7 @@ void vlapic_reg_write(struct vcpu *v, unsigned int reg, uint32_t val) >> if ( vlapic_sw_disabled(vlapic) ) >> val |= APIC_LVT_MASKED; >> val &= array_access_nospec(vlapic_lvt_mask, (reg - APIC_LVTT) >> 4); >> + val &= ~(APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING); > > There shouldn't be a 2nd &= here; what needs adding should imo be added to > (really: removed from) vlapic_lvt_mask[]. I'll try it. (Orthogonal to this I wonder whether > guest_wrmsr_x2apic() wouldn't better use that array, too.) WRMSR checks for MBZ. RO bits are not MBZ, so masks are different. > > While looking at this, don't we have an issue with CMCI as well? I see no APIC_CMCI write emulation. only read. > guest_{rd,wr}msr_x2apic() handle it, but vlapic_reg_write() doesn't. I.e. on > AMD we would fail to deliver #GP when the guest accesses it, while on Intel > we would lose the value written. And we also don't set its mask bit in > vlapic_do_init(). I guess I need to make a patch ... Is'n it depends on CMCI capability exposing to guest? (have no idea what's CMCI :) -- Best regards, -grygorii