From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout.efficios.com (smtpout.efficios.com [167.114.26.122]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D772A149C6D for ; Fri, 27 Sep 2024 15:24:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=167.114.26.122 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727450655; cv=none; b=BQTN1vqOQiW9akpnc5FFj7PsI/gxAooMpHISBBoCJn1Kl6FH4W3XKWQfUuxBP70YtXXkhEyRCWxVq1QZJBdnx8HGEtsISTBuWlD5I6PCkhNzdrm1y9/v/8Gv4PEm12LqmsOuoTNGWA++D+4Pe2Fs8zHU4Jm7LIEB+87oa9NQDbY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727450655; c=relaxed/simple; bh=tFhKGedYSLt2FB/2OyeFSMYVEXgh7bqsTO9vhWhnYQc=; h=Message-ID:Date:MIME-Version:Subject:From:To:Cc:References: In-Reply-To:Content-Type; b=qvCrJkrvdEON3vsZ9iwc3zqX0ObPDWAaKwlk2w9nUucchBXbQ2wVtzaTvsb/OC0GflBiyIEcua3CrZjBzvzVeGPz9YG5kmIcJfluqRnlnh3K86ysHCvBWmg4efM+yH8c8gANw6EMSB5gouoy5balStW0RPjDSfgV97heh1Imsa8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=efficios.com; spf=pass smtp.mailfrom=efficios.com; dkim=pass (2048-bit key) header.d=efficios.com header.i=@efficios.com header.b=UMjDRB8g; arc=none smtp.client-ip=167.114.26.122 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=efficios.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=efficios.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=efficios.com header.i=@efficios.com header.b="UMjDRB8g" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=efficios.com; s=smtpout1; t=1727450652; bh=tFhKGedYSLt2FB/2OyeFSMYVEXgh7bqsTO9vhWhnYQc=; h=Date:Subject:From:To:Cc:References:In-Reply-To:From; b=UMjDRB8g9Od4LQQDbOo2DhG9D9mt3ujSTm1Ik0H31/GWwOyoPmPLGh1scv+CqygLK E8qlAlChVX4SZ9rvHVOUsmp57qGTWaoFB4FZCC4eZRxA40es1W4kbDic6DdClNcRov fcwV4IM9Sxib2xf5gJi10EDbShKkwu16sIoVh6FcXEXMffg4tktJW+jIZ7CGdd6o9s YsOjBQJWIMXqc4STmXaotKTCwsxgvsi/oNKbU3nsGHYdCtLRYZQN8iXYIAq6HVSNSu ZXRYhVNzekv5rasLIttlSdN5KJJ5x4fgTLuI7gjlYdCO7vOEy2V4VS9OJEIHnonFXx Qt0fNe0ndqlmg== Received: from [IPV6:2606:6d00:100:4000:cacb:9855:de1f:ded2] (unknown [IPv6:2606:6d00:100:4000:cacb:9855:de1f:ded2]) by smtpout.efficios.com (Postfix) with ESMTPSA id 4XFZ4r3svSz1PNM; Fri, 27 Sep 2024 11:24:12 -0400 (EDT) Message-ID: Date: Fri, 27 Sep 2024 11:22:07 -0400 Precedence: bulk X-Mailing-List: lkmm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 1/4] hazptr: Add initial implementation of hazard pointers From: Mathieu Desnoyers To: Boqun Feng , Linus Torvalds Cc: Jonas Oberhauser , linux-kernel@vger.kernel.org, rcu@vger.kernel.org, linux-mm@kvack.org, lkmm@lists.linux.dev, "Paul E. McKenney" , Frederic Weisbecker , Neeraj Upadhyay , Joel Fernandes , Josh Triplett , "Uladzislau Rezki (Sony)" , rostedt , Lai Jiangshan , Zqiang , Peter Zijlstra , Ingo Molnar , Will Deacon , Waiman Long , Mark Rutland , Thomas Gleixner , Kent Overstreet , Vlastimil Babka , maged.michael@gmail.com, Neeraj Upadhyay References: <48992c9f-6c61-4716-977c-66e946adb399@efficios.com> <2b2aea37-06fe-40cb-8458-9408406ebda6@efficios.com> <55633835-242c-4d7f-875b-24b16f17939c@huaweicloud.com> <54487a36-f74c-46c3-aed7-fc86eaaa9ca2@huaweicloud.com> <0b262fe5-2fc5-478d-bf66-f208723238d5@efficios.com> <8aceaf4f-5578-4fca-8be7-3448d7b89721@efficios.com> <08423acb-1f8e-407a-80fe-c424c6ee2861@efficios.com> Content-Language: en-US In-Reply-To: <08423acb-1f8e-407a-80fe-c424c6ee2861@efficios.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 2024-09-27 16:43, Mathieu Desnoyers wrote: > On 2024-09-27 12:59, Mathieu Desnoyers wrote: >> On 2024-09-27 06:28, Boqun Feng wrote: > [...] >>> I replaced ADDRESS_EQ(a, b) with ADDRESS_EQ(b, a), and the compile >>> result shows it can prevent the issue: >> >> I see, yes. It prevents the issue by making the compiler create >> a copy of the value "modified" by the asm before doing the equality >> comparison. >> >> This means the compiler cannot derive the value for b from the first >> load when b is used after after the equality comparison. >> >> The only downside of OPTIMIZER_HIDE_VAR() is that it adds an extra >> "mov" instruction to move the content across registers. I don't think >> it matters performance wise though, so that solution is appealing >> because it is arch-agnostic. >> >> One small improvement over your proposed solution would be to apply >> OPTIMIZER_HIDE_VAR() on both inputs. Because this is not a volatile >> asm, it is simply optimized away if var1 or var2 is unused following >> the equality comparison. It is more convenient to prevent replacement >> of both addresses being compared by the other rather than providing >> the guarantee only on a single parameter: > > Actually, your approach is better (only preserving the address > dependency on the first parameter), because it allows the second > parameter to be a constant. > > Here is a diff. Please let me know if I need to improve anything wrt > comments or implementation: > > diff --git a/include/linux/compiler.h b/include/linux/compiler.h > index 2df665fa2964..52434eccd715 100644 > --- a/include/linux/compiler.h > +++ b/include/linux/compiler.h > @@ -186,6 +186,32 @@ void ftrace_likely_update(struct ftrace_likely_data > *f, int val, >      __asm__ ("" : "=r" (var) : "0" (var)) >  #endif > > +/* > + * Compare an address with an expression while preserving the address > + * dependencies for later use of the address. It should be used when > + * comparing an address returned by rcu_dereference() with another > + * address (either constant or in registers). > + * > + * This is needed to prevent the compiler SSA GVN optimization pass from > + * replacing the register holding @addr by @expr (either a constant or a Actually, I've done a bit on testing on godbolt, and it appears that disabling this specific optimization makes the problem disappear: -fcse-follow-jumps (by use of -fno-cse-follow-jumps). I will update this comment to state that both CSE and SSA GVN optimizations can cause issues there. Thanks, Mathieu > + * register) based on their equality, which does not preserve address > + * dependencies and allows the following misordering speculations: > + * > + * - If @expr is a constant, the compiler can issue the loads which depend > + *   on @addr before the load of @addr. > + * - If @expr is a register populated by a prior load, weakly-ordered > + *   CPUs can speculate loads which depend on @addr before the load of the > + *   address they depend on. > + */ > +#ifndef ADDRESS_EQ > +#define ADDRESS_EQ(addr, expr)                    \ > +    ({                            \ > +        bool __res = (addr) == (expr);            \ > +        OPTIMIZER_HIDE_VAR(addr);            \ > +        __res;                        \ > +    }) > +#endif > + >  #define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), > __COUNTER__) > >  /** > -- Mathieu Desnoyers EfficiOS Inc. https://www.efficios.com