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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: linux-renesas-soc@vger.kernel.org,
	Magnus Damm <magnus.damm@gmail.com>,
	Gareth Williams <gareth.williams.jx@renesas.com>,
	Phil Edworthy <phil.edworthy@renesas.com>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Vinod Koul <vkoul@kernel.org>,
	dmaengine@vger.kernel.org,
	Milan Stevanovic <milan.stevanovic@se.com>,
	Jimmy Lalande <jimmy.lalande@se.com>,
	Pascal Eberhard <pascal.eberhard@se.com>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Herve Codina <herve.codina@bootlin.com>,
	Clement Leger <clement.leger@bootlin.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	linux-clk@vger.kernel.org, Viresh Kumar <vireshk@kernel.org>,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Subject: Re: [PATCH v6 5/8] dmaengine: dw: dmamux: Introduce RZN1 DMA router support
Date: Mon, 4 Apr 2022 17:03:28 +0300 (EEST)	[thread overview]
Message-ID: <f76c2e68-2a4a-381a-3c40-eb369a08550@linux.intel.com> (raw)
In-Reply-To: <20220404133904.1296258-6-miquel.raynal@bootlin.com>

On Mon, 4 Apr 2022, Miquel Raynal wrote:

> The Renesas RZN1 DMA IP is based on a DW core, with eg. an additional
> dmamux register located in the system control area which can take up to
> 32 requests (16 per DMA controller). Each DMA channel can be wired to
> two different peripherals.
> 
> We need two additional information from the 'dmas' property: the channel
> (bit in the dmamux register) that must be accessed and the value of the
> mux for this channel.
> 
> Aside from the driver introduction, as these devices are described as
> subnodes of the system controller, we also need the system controller
> (clock) driver to populate its children manually. Starting from now on,
> one child can be the dmamux.
> 
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---

> +static void *rzn1_dmamux_route_allocate(struct of_phandle_args *dma_spec,
> +					struct of_dma *ofdma)
> +{
> +	struct platform_device *pdev = of_find_device_by_node(ofdma->of_node);
> +	struct rzn1_dmamux_data *dmamux = platform_get_drvdata(pdev);
> +	struct rzn1_dmamux_map *map;
> +	unsigned int dmac_idx, chan, val;
> +	u32 mask;
> +	int ret;
> +
> +	if (dma_spec->args_count != 6)
> +		return ERR_PTR(-EINVAL);
> +
> +	map = kzalloc(sizeof(*map), GFP_KERNEL);
> +	if (!map)
> +		return ERR_PTR(-ENOMEM);
> +
> +	chan = dma_spec->args[0];
> +	map->req_idx = dma_spec->args[4];
> +	val = dma_spec->args[5];
> +	dma_spec->args_count -= 2;
> +
> +	if (chan >= RZN1_DMAMUX_SPLIT) {
> +		dev_err(&pdev->dev, "Invalid DMA request line: %u\n", chan);
> +		ret = -EINVAL;
> +		goto free_map;
> +	}
> +
> +	if (map->req_idx >= RZN1_DMAMUX_LINES ||
> +	    (map->req_idx % RZN1_DMAMUX_SPLIT) != chan) {
> +		dev_err(&pdev->dev, "Invalid MUX request line: %u\n", map->req_idx);
> +		ret = -EINVAL;
> +		goto free_map;
> +	}
> +
> +	dmac_idx = map->req_idx < RZN1_DMAMUX_SPLIT ? 0 : 1;
> +	dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", dmac_idx);
> +	if (!dma_spec->np) {
> +		dev_err(&pdev->dev, "Can't get DMA master\n");
> +		ret = -EINVAL;
> +		goto free_map;
> +	}
> +
> +	dev_dbg(&pdev->dev, "Mapping DMAMUX request %u to DMAC%u request %u\n",
> +		map->req_idx, dmac_idx, chan);
> +
> +	mask = BIT(map->req_idx);
> +	mutex_lock(&dmamux->lock);
> +	dmamux->used_chans |= mask;
> +	ret = r9a06g032_sysctrl_set_dmamux(mask, val ? mask : 0);
> +	mutex_unlock(&dmamux->lock);
> +	if (ret)
> +		goto free_mux;

Move this check before the unlock. Then free_mux path doesn't need to do
(re)lock as the mutex is still held. You might also want to consider 
renaming the label e.g. to chan_release_and_unlock.

> +
> +	return map;
> +
> +free_mux:
> +	mutex_lock(&dmamux->lock);
> +	dmamux->used_chans &= ~mask;
> +	mutex_unlock(&dmamux->lock);
> +free_map:
> +	kfree(map);
> +
> +	return ERR_PTR(ret);
> +}


-- 
 i.


  reply	other threads:[~2022-04-04 14:03 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-04 13:38 [PATCH v6 0/8] RZN1 DMA support Miquel Raynal
2022-04-04 13:38 ` [PATCH v6 1/8] dt-bindings: dmaengine: Introduce RZN1 dmamux bindings Miquel Raynal
2022-04-04 13:38 ` [PATCH v6 2/8] dt-bindings: clock: r9a06g032-sysctrl: Reference the DMAMUX subnode Miquel Raynal
2022-04-04 13:38 ` [PATCH v6 3/8] dt-bindings: dmaengine: Introduce RZN1 DMA compatible Miquel Raynal
2022-04-04 13:39 ` [PATCH v6 4/8] soc: renesas: rzn1-sysc: Export function to set dmamux Miquel Raynal
2022-04-04 13:39 ` [PATCH v6 5/8] dmaengine: dw: dmamux: Introduce RZN1 DMA router support Miquel Raynal
2022-04-04 14:03   ` Ilpo Järvinen [this message]
2022-04-05  5:57   ` Vinod Koul
2022-04-05  7:07     ` Andy Shevchenko
2022-04-05  9:18       ` Vinod Koul
2022-04-04 13:39 ` [PATCH v6 6/8] dmaengine: dw: Add RZN1 compatible Miquel Raynal
2022-04-04 13:39 ` [PATCH v6 7/8] ARM: dts: r9a06g032: Add the two DMA nodes Miquel Raynal
2022-04-04 13:39 ` [PATCH v6 8/8] ARM: dts: r9a06g032: Describe the DMA router Miquel Raynal
2022-04-04 14:48 ` [PATCH v6 0/8] RZN1 DMA support Geert Uytterhoeven
2022-04-04 15:01   ` Miquel Raynal

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