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Tue, 27 May 2025 15:01:39 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id BEE874006A; Tue, 27 May 2025 15:00:19 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 75DA8AD0024; Tue, 27 May 2025 14:59:58 +0200 (CEST) Received: from [10.48.87.62] (10.48.87.62) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 27 May 2025 14:59:58 +0200 Message-ID: Date: Tue, 27 May 2025 14:59:57 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 01/10] arm: mach-stm32: stm32h7: add initial lowlevel early function To: Johannes Krottmayer , CC: Patrick Delaunay References: <611b339e-a9fe-4cc1-b2fc-617d844a86ac@krotti42.com> <20250508212058.640483-2-johannes@krotti42.com> Content-Language: en-US From: Patrice CHOTARD In-Reply-To: <20250508212058.640483-2-johannes@krotti42.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.48.87.62] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-27_06,2025-05-27_01,2025-03-28_01 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On 5/8/25 23:23, Johannes Krottmayer wrote: > Add new assembly function 'arch_very_early_init' > > This functions setups the power supply for STM32H7 SoC's to > direct SMPS mode, which is required for some boards like > the STM32H747I-DISCO in the default configuration. > > If this isn't done in an early stage it cause a deadlock and > also the SoC is running in a limited mode according to the > TRM from the SoC. > > Signed-off-by: Johannes Krottmayer > Cc: Patrick Delaunay > Cc: Patrice Chotard > --- > arch/arm/mach-stm32/stm32h7/lowlevel.S | 45 ++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) > create mode 100644 arch/arm/mach-stm32/stm32h7/lowlevel.S > > diff --git a/arch/arm/mach-stm32/stm32h7/lowlevel.S b/arch/arm/mach-stm32/stm32h7/lowlevel.S > new file mode 100644 > index 00000000000..97f4e383e3b > --- /dev/null > +++ b/arch/arm/mach-stm32/stm32h7/lowlevel.S > @@ -0,0 +1,45 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (C) 2025, Johannes Krottmayer > + */ > + > +#include > + > +/* > + * STM32H7 PWR registers > + */ > +#define PWR_CR3 0x5802480C > +#define PWR_CR3_LDOEN 1 > + > +#define PWR_CSR1 0x58024804 > +#define PWR_CSR1_ACTVOSRDY 13 > + > +ENTRY(arch_very_early_init) > + /* > + * Setup power supply for STM32H7 to direct SMPS mode. > + * This is the default configuration from some boards > + * like the SMT32H747i-DISCO. > + * > + * If these steps will not be done, this cause a deadlock. > + */ > + ldr r6, =PWR_CR3 > + /* Disable LDO */ > + movs r0, #1 > + lsl r1, r0, #PWR_CR3_LDOEN > + mvn r2, r1 > + ldr r3, [r6] > + and r3, r2 > + str r3, [r6] > + lsl r1, r0, #PWR_CSR1_ACTVOSRDY > + > + /* Loop until ACTVOSRDY is valid */ > +1: > + ldr r6, =PWR_CSR1 > + ldr r3, [r6] > + and r3, r1 > + cmp r3, r1 > + bne 1b > + > + /* Jump back to C runtime setup */ > + bx lr > +ENDPROC(arch_very_early_init) Hi Johannes Reviewed-by: Patrice Chotard Thanks Patrice