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Mon, 17 Nov 2025 05:53:36 -0800 (PST) Received: from [192.168.68.110] ([191.202.237.26]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4508a6c1510sm4285905b6e.18.2025.11.17.05.53.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Nov 2025 05:53:34 -0800 (PST) Message-ID: Date: Mon, 17 Nov 2025 10:53:30 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] target/riscv: Update MISA.X for non-standard extensions To: frank.chang@sifive.com, qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , "open list:RISC-V TCG CPUs" , Max Chou References: <20251114090134.1125646-1-frank.chang@sifive.com> <20251114090134.1125646-3-frank.chang@sifive.com> From: Daniel Henrique Barboza Content-Language: en-US In-Reply-To: <20251114090134.1125646-3-frank.chang@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 11/14/25 6:01 AM, frank.chang@sifive.com wrote: > From: Frank Chang > > MISA.X is set if there are any non-standard extensions. > We should set MISA.X when any of the vendor extensions is enabled. > > Signed-off-by: Frank Chang > Reviewed-by: Max Chou > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/cpu.h | 1 + > target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++ > 2 files changed, 16 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 8899bf7667a..2e0c92fe593 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -69,6 +69,7 @@ typedef struct CPUArchState CPURISCVState; > #define RVH RV('H') > #define RVG RV('G') > #define RVB RV('B') > +#define RVX RV('X') > > extern const uint32_t misa_bits[]; > const char *riscv_get_misa_ext_name(uint32_t bit); > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index da09a2417cc..0d730f4d774 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -1180,6 +1180,20 @@ static void riscv_cpu_update_misa_c(RISCVCPU *cpu) > } > } > > +/* MISA.X is set when any of the non-standard extensions is enabled. */ > +static void riscv_cpu_update_misa_x(RISCVCPU *cpu) > +{ > + CPURISCVState *env = &cpu->env; > + const RISCVCPUMultiExtConfig *arr = riscv_cpu_vendor_exts; > + > + for (int i = 0; arr[i].name != NULL; i++) { > + if (isa_ext_is_enabled(cpu, arr[i].offset)) { > + riscv_cpu_set_misa_ext(env, env->misa_ext | RVX); > + break; > + } > + } > +} > + > void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > { > CPURISCVState *env = &cpu->env; > @@ -1188,6 +1202,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > riscv_cpu_init_implied_exts_rules(); > riscv_cpu_enable_implied_rules(cpu); > riscv_cpu_update_misa_c(cpu); > + riscv_cpu_update_misa_x(cpu); > > riscv_cpu_validate_misa_priv(env, &local_err); > if (local_err != NULL) {