From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [PATCH] drm/i915: Use PIPE_CONTROL for flushing on
	gen6+.
Date: Mon, 26 Sep 2011 20:43:50 +0100
Message-ID: <f80fcd$20ga0a@fmsmga001.fm.intel.com>
References: <1317063563-1526-1-git-send-email-kenneth@whitecape.org>
	<d08817$1l8egs@azsmga001.ch.intel.com>
	<20110926192302.GC2804@phenom.ffwll.local>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from mga01.intel.com (mga01.intel.com [192.55.52.88])
	by gabe.freedesktop.org (Postfix) with ESMTP id 1863AA0883
	for <intel-gfx@lists.freedesktop.org>;
	Mon, 26 Sep 2011 12:44:04 -0700 (PDT)
In-Reply-To: <20110926192302.GC2804@phenom.ffwll.local>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Mon, 26 Sep 2011 21:23:02 +0200, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Mon, Sep 26, 2011 at 08:16:04PM +0100, Chris Wilson wrote:
> > On Mon, 26 Sep 2011 11:59:23 -0700, Kenneth Graunke <kenneth@whitecape.org> wrote:
> > > From: Jesse Barnes <jbarnes@virtuousgeek.org>
> > 
> > From the school of "If ain't broke, don't fix it" there needs to be a real
> > explanation of why this change is required here.
> > 
> > PIPE_CONTROL and its workarounds is a very bitter pill to swallow if
> > MI_FLUSH continues to function.
> 
> Lazy tlb flush, gfdt flush, seperate depth cache flush. In short, I want
> this ;-)

I feel jaded, I could have swore you just said "bug, bugs, bugs." ;-)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre