From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 1/3] drm/i915: swizzling support for snb/ivb Date: Wed, 01 Feb 2012 22:26:08 +0000 Message-ID: References: <1328024876-5240-1-git-send-email-daniel.vetter@ffwll.ch> <4F29B012.4060905@bwidawsk.net> <20120201221619.GC8395@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id AC0DFA0DB0 for ; Wed, 1 Feb 2012 14:26:13 -0800 (PST) In-Reply-To: <20120201221619.GC8395@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter , Ben Widawsky Cc: Daniel Vetter , Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Wed, 1 Feb 2012 23:16:19 +0100, Daniel Vetter wrote: > On Wed, Feb 01, 2012 at 01:35:14PM -0800, Ben Widawsky wrote: > > You didn't address one questions I really cared about, how is it safe to > > ignore channel 3 size? While I'm at it, I wonder what is in these > > registers if you have less than 256MB. If the answer is zero, then your > > check isn't safe enough below. > > Hm, I've thought I've answered that in the mail to your review: 3 channel > ddr configurations only exists on i7 chips without a gpu attached. > Furthermore swizzling is only sensible when we have 2 channels anyway. It almost always sensible to leave a comment behind in the code to address review questions. What may not appear immediately obvious to another person is unlikely to occur to anyone perusing the code 18+ months later. Didn't future Daniel warn you about that when he travelled back from December 2012? :) -Chris -- Chris Wilson, Intel Open Source Technology Centre