From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 2/2] drm/i915: add an explict mmio base for gpio/gmbus io Date: Fri, 23 Mar 2012 23:01:31 +0000 Message-ID: References: <1332542616-2367-1-git-send-email-daniel.vetter@ffwll.ch> <1332542616-2367-2-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 122A59E7E2 for ; Fri, 23 Mar 2012 16:01:38 -0700 (PDT) In-Reply-To: <1332542616-2367-2-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Fri, 23 Mar 2012 23:43:36 +0100, Daniel Vetter wrote: > Again, Valleyview modes these around, so make the mmio base more > explicit to consolidate the base address computations to one > HAS_PCH_SPLIT check. > > Signed-Off-by: Daniel Vetter Consolidating the offset computation is nice. Everytime I look at this I question whether we should be using GMBUS0 or a plain 0 for the actual registers. I think GMBUS0 wins for being greppable. Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre