From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH fixes] drm/i915: Fix unfenced alignment on pre-G33 hardware Date: Mon, 06 Jun 2011 21:56:51 +0100 Message-ID: References: <1307369924-3601-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 176149E79D for ; Mon, 6 Jun 2011 13:56:58 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Keith Packard , intel-gfx@lists.freedesktop.org Cc: stable@kernel.org List-Id: intel-gfx@lists.freedesktop.org On Mon, 06 Jun 2011 11:09:30 -0700, Keith Packard wrote: > On Mon, 06 Jun 2011 18:50:16 +0100, Chris Wilson wrote: > > > Hah. Anyway it is actually irrelevant as it turns out, the kernel is broken > > with any per-surface tiling on gen2/gen3. > > Right, seems like we need to signal user space that tiling works now, > which should involve a new ioctl of some form? So PARAM_HAS_PER_SURFACE_TILING and re-enable fencing for render operations on gen2/3. > > Yes, I can. But the simple bug fix doesn't fix anything without the other > > chunk. Do you still want it split? > > Isn't it a general bug? We're asking for an alignment value using the > wrong tiling mode when changing tiling modes. Indeed. I just can't test the patch independently since the hangs look identical. -Chris -- Chris Wilson, Intel Open Source Technology Centre