From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: set cache sharing policy to max sharing on SNB+ Date: Sat, 02 Jul 2011 08:20:39 +0100 Message-ID: References: <1309563307-5480-1-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 303729E776 for ; Sat, 2 Jul 2011 00:20:42 -0700 (PDT) In-Reply-To: <1309563307-5480-1-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, 1 Jul 2011 16:35:07 -0700, Jesse Barnes wrote: > By default, the GPU will only share a very small portion of the CPU > cache. With this change, both the GPU and CPU will have full access to > the cache, which should help (sometimes a lot) in most cases. What's the trade off? Is the GPU data in the cache treated differently than CPU data when it comes to cache eviction and so this asymmetrically hurts CPU bound applications? At the least it will force more CPU data out of the cache, which will be enough to make some people scream and howl. Do we want to expose this as a parameter whilst we test various configurations? Is this just yet a another step on the path to a coordinated cpu-gpu governor? -Chris -- Chris Wilson, Intel Open Source Technology Centre