From: Helen Koike <koike@igalia.com>
To: Andi Shyti <andi.shyti@kernel.org>
Cc: rodrigo.vivi@intel.com, demarchi@kernel.org,
intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
tvrtko.ursulin@igalia.com, linux-kernel@vger.kernel.org,
kernel-dev@igalia.com
Subject: Re: [PATCH v2] drm/xe/lrc: Restore CTX_CS_INDIRECT_CTX_OFFSET programming for ADL
Date: Thu, 1 Oct 2026 15:00:03 -0300 [thread overview]
Message-ID: <f852acbe-6d4c-4edb-a320-e2d690486bd6@igalia.com> (raw)
In-Reply-To: <ar3_LjzklapoN1tM@zenone.zhora.eu>
Hi Andi,
Thanks for your reply.
On 10/1/26 5:45 AM, Andi Shyti wrote:
> Hi Helen,
>
> On Wed, Sep 30, 2026 at 02:04:30PM -0300, Helen Koike wrote:
>> CTX_CS_INDIRECT_CTX_OFFSET default value is not retrieved from the GPU
>> by inhibit+context save mechanism since it is not part of the Engine
>> Context. Thus, at restore, 0x0 is programed back to the GPU, which is
>
> /programed/programmed/
Ack
>
>> an invalid value according to the PRM.
>
> ...
>
>> /*
>> * Enable INDIRECT_CTX leaving INDIRECT_CTX_OFFSET at its default: it
>> - * varies per engine class, but the default is good enough
>> + * varies per engine class, but the default is good enough, except on
>> + * Alder Lake.
>> */
>> xe_lrc_write_ctx_reg(lrc,
>> CTX_CS_INDIRECT_CTX,
>> (xe_bo_ggtt_addr(lrc->bo) + state.offset) |
>> /* Size in CLs. */
>> (state.written * sizeof(u32) / 64));
>> + if (GRAPHICS_VER(lrc_to_xe(lrc)) < 20)
>
> Are you assuming that only Alder Lake is xe < 20?
This is a good point, since I was basing this patch on TGL PRM [1], I
believe it should apply to all Gen12 gpus. Maybe I could s/for ADL/for
Gen12, make sense? I only tested on ADL though.
[1]
https://www.intel.com/content/www/us/en/docs/graphics-for-linux/developer-reference/1-0/tiger-lake.html
>
> As you are restoring the original code for render and compute,
> would it make sense also add a check for class being
> XE_EGINE_CLASS_RENDER || XE_ENGINE_CLASS_COMPUTE?
In my understanding from commit [2], indirect ctx will be allowed for
other engines in the future, so I'm not sure we should limit here to
those classes besides what gt_engine_needs_indirect_ctx() does.
[2]
https://lore.kernel.org/all/20250916-wa-bb-cmds-v5-5-306bddbc15da@intel.com/
Helen
>
> Andi
>
>> + xe_lrc_write_ctx_reg(lrc,
>> + CTX_CS_INDIRECT_CTX_OFFSET,
>> + CTX_INDIRECT_CTX_OFFSET_DEFAULT);
>>
>> return 0;
>> }
>> --
>> 2.54.0
>>
prev parent reply other threads:[~2026-10-01 18:00 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-30 17:04 [PATCH v2] drm/xe/lrc: Restore CTX_CS_INDIRECT_CTX_OFFSET programming for ADL Helen Koike
2026-09-30 17:14 ` sashiko-bot
2026-09-30 17:38 ` ✓ CI.KUnit: success for " Patchwork
2026-09-30 19:28 ` ✓ Xe.CI.BAT: " Patchwork
2026-09-30 23:29 ` [PATCH v2] " Matt Roper
2026-10-01 14:17 ` Helen Koike
2026-10-01 1:11 ` ✗ Xe.CI.FULL: failure for " Patchwork
2026-10-01 8:45 ` [PATCH v2] " Andi Shyti
2026-10-01 18:00 ` Helen Koike [this message]
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