From: shuang.he@intel.com
To: shuang.he@intel.com, ethan.gao@intel.com,
intel-gfx@lists.freedesktop.org, ville.syrjala@linux.intel.com
Subject: Re: [PATCH 7/7] drm/i915: Throw out WIP CHV power well definitions
Date: 10 Apr 2015 16:09:10 -0700 [thread overview]
Message-ID: <f90827$k726pt@orsmga001.jf.intel.com> (raw)
In-Reply-To: <1428679293-6208-8-git-send-email-ville.syrjala@linux.intel.com>
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6177
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -7 276/276 269/276
ILK 301/301 301/301
SNB -1 316/316 315/316
IVB -1 328/328 327/328
BYT 285/285 285/285
HSW 394/394 394/394
BDW 321/321 321/321
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*PNV igt@gem_tiled_pread_pwrite PASS(3) FAIL(1)PASS(1)
PNV igt@gem_userptr_blits@coherency-sync CRASH(2)PASS(3) CRASH(1)PASS(1)
PNV igt@gem_userptr_blits@coherency-unsync CRASH(2)PASS(3) CRASH(2)
PNV igt@gen3_render_linear_blits FAIL(4)PASS(3) FAIL(2)
PNV igt@gen3_render_mixed_blits FAIL(3)PASS(3) FAIL(1)PASS(1)
PNV igt@gen3_render_tiledx_blits FAIL(4)PASS(3) FAIL(2)
PNV igt@gen3_render_tiledy_blits FAIL(4)PASS(3) FAIL(2)
*SNB igt@kms_flip@dpms-vs-vblank-race PASS(5) DMESG_WARN(2)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_start_link_train[i915]]*ERROR*failed_to_update_link_training@failed to update link training
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_get_link_status@failed to get link status
IVB igt@gem_pwrite_pread@uncached-copy-performance DMESG_WARN(1)PASS(3) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck timer elapsed... blitter ring idle
Note: You need to pay more attention to line start with '*'
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next prev parent reply other threads:[~2015-04-10 23:09 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-10 15:21 [PATCH 0/7] drm/i915: CHV DPIO power gating stuff ville.syrjala
2015-04-10 15:21 ` [PATCH 1/7] drm/i915: Implement chv display PHY lane stagger setup ville.syrjala
2015-05-08 12:26 ` Deepak S
2015-04-10 15:21 ` [PATCH 2/7] drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV ville.syrjala
2015-05-08 12:54 ` Deepak S
2015-05-08 13:19 ` Ville Syrjälä
2015-05-08 13:33 ` Deepak S
2015-05-08 13:57 ` Daniel Vetter
2015-04-10 15:21 ` [PATCH 3/7] Revert "drm/i915: Hack to tie both common lanes together on chv" ville.syrjala
2015-05-08 12:55 ` Deepak S
2015-04-10 15:21 ` [PATCH 4/7] drm/i915: Use the default 600ns LDO programming sequence delay ville.syrjala
2015-05-08 13:01 ` Deepak S
2015-05-08 13:22 ` Ville Syrjälä
2015-05-08 13:35 ` Deepak S
2015-04-10 15:21 ` [PATCH 5/7] drm/i915: Only wait for required lanes in vlv_wait_port_ready() ville.syrjala
2015-05-08 13:53 ` Deepak S
2015-05-08 14:27 ` Daniel Vetter
2015-04-10 15:21 ` [PATCH 6/7] drm/i915: Implement PHY lane power gating for CHV ville.syrjala
2015-05-08 14:49 ` Deepak S
2015-05-08 16:05 ` Ville Syrjälä
2015-05-09 5:35 ` Deepak S
2015-05-11 11:43 ` Ville Syrjälä
2015-05-13 3:19 ` Deepak S
2015-04-10 15:21 ` [PATCH 7/7] drm/i915: Throw out WIP CHV power well definitions ville.syrjala
2015-04-10 23:09 ` shuang.he [this message]
2015-05-08 14:58 ` Deepak S
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